Job Details:
Job Description:
Position Overview
You will work alongside senior engineers to build testbenches, write constrained-random tests, close functional coverage, and root-cause simulation failures - developing end-to-end verification skills from day one.
We look for engineers who think algorithmically, write clean code, and are excited to apply the latest AI-assisted development tools as a core part of how they work. You do not need to know everything on day one; you do need strong fundamentals, genuine curiosity, and the drive to ramp fast.
Key Responsibilities
• Develop testbench components, constrained-random stimulus, and functional checkers for interconnect and chassis IP under guidance of senior engineers
• Write, run, and debug simulation tests; analyze failures and root-cause issues to closure with clear technical write-ups
• Contribute to functional coverage plans, coverage closure analysis, and regression triage
• Participate in spec reviews, design discussions, and bug triage; learn to contribute across architecture, design, and software boundaries
• Use AI-assisted coding and debugging tools as an everyday part of development workflow; actively contribute to the team's productivity through automation and scripting
• Continuously build depth in hardware design, verification methodology, and the chip development flow
What We're Looking For
You should demonstrate the following professional traits to be successful:
• Genuine curiosity and the drive to ramp fast
• Algorithmic thinking with a commitment to writing clean code
• Enthusiasm for applying the latest AI-assisted development tools as a core part of how you work
Qualifications:
This position is not eligible for Intel immigration sponsorship.
Minimum Qualifications
• BS or MS in Electrical Engineering, Computer Engineering, or Computer Science and 3+ months of Internship experience in a hardware design or verification environment
• Foundation in logic design and digital circuits - required; ability to read and reason about RTL is essential
• Demonstrated algorithmic thinking and software fundamentals application - required
• Demonstrated proficiency in at least one of C/C++, Python, or SystemVerilog through coursework, projects, or internships
• Coursework or project exposure to two or more of the following: computer architecture, parallel and distributed computing, operating systems, hardware/software interfaces, VLSI design
• Demonstrated use of AI coding assistants as a regular part of coursework or project work - not occasional use, but as a genuine productivity tool
Preferred Qualifications
• Coursework or project work in hardware verification, FPGA design, or RTL simulation (ModelSim, VCS, Questa, or similar)
• Exposure to SystemVerilog, UVM concepts, or assertion-based verification through coursework, self-study, or internship
• Familiarity with standard bus protocols (AXI, AHB, PCIe) or cache/memory hierarchy concepts
• Demonstrated project work (senior design, research, hackathon, personal) involving hardware modeling, algorithm implementation in HDL, or hardware-software co-design
• Comfort working in Linux environments, using version control (git), and writing build/test automation scripts
• Worked experience in any related field
Job Type:
College Grad
Shift:
Shift 1 (United States of America)
Primary Location:
US, California, Santa Clara
Additional Locations:
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $105,650.00-149,150.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
