Cadence Design Systems

Design Verification Architect / Director

Cadence Design Systems$185K — $344K *
Telecommunications & Hardware
15+ years of experience
Job Overview by Ladders

Qualifications

  • 17+ years of design verification experience
  • Bachelor's degree or higher in Electrical Engineering or Computer Engineering
  • Proven experience leading and managing teams
  • Strong managerial, leadership, and interpersonal skills
  • Excellent knowledge of computer architecture and design verification fundamentals
  • Thorough understanding of System Verilog, UVM, and other programming languages
  • Experience with assembly language programming required

Responsibilities

  • Lead and manage the Processor Verification team
  • Verify microprocessor cores and their peripherals
  • Craft and execute verification plans for complex CPU designs
  • Implement simulation or emulation testbenches and diagnostics
  • Collect and close coverage metrics
  • Collaborate with cross-functional teams to ensure coverage scope
  • Track and report the progress of a team of 7-10 engineers

Benefits

  • Paid vacation and paid holidays
  • 401(k) plan with employer match
  • Employee stock purchase plan
  • Variety of medical, dental, and vision plan options
Full Job Description
Location

San Jose, CA and Austin, TX

Job Description

Responsibilities

As a Design Verification Team Director, lead and run the Processor Verification team, you will be responsible for the verification of microprocessor cores and their peripherals

Relevant experience in-order/out-of-order CPU cores and memory subsystem strongly preferred

Crafting verification plans and executing them to verify highly complex CPU designs.

You will implement simulation or emulation testbenches, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target verification goals.

You will be responsible for coverage collection and closure

You will work closely with cross-functional teams (DV/Arch/Design/FW) to identify coverage scope

Tracking and reporting the work of 7-10 engineers

Required Skills and Experience:

17+ years of design verification experience

BS (or higher) in EE/Computer Engineering

Proven experience at leading/managing team.

Strong managerial, leadership and interpersonal skills

Excellent knowledge of computer architecture and design verification fundamentals

Thorough understanding of System Verilog, UVM, and other programming languages to build flexible and reusable complex testbenches

Exposure to scripting languages like Perl, Unix shell or similar languages

Experience with assembly language programming required

Experience with Formal Verification will be a plus

Experience with the development of fully automated flows

Experience with Gate Level Simulations

Excellent written and oral communication skills necessary

Knowledge of processor verification required

The annual salary range for California is $185,500 to $344,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

About Cadence Design Systems

Cadence Design Systems, Inc. is an American multinational electronic design automation software and engineering services company, founded in 1988 by the merger of SDA Systems and ECAD, Inc. The company produces software, hardware and silicon structures for designing integrated circuits, systems on chips (SoCs) and printed circuit boards.
Learn more about Cadence Design Systems
Size
9,300 employees
Market Cap
$43.9 billion
Industry
Net Income
$590.6 million
Founded
2018
5 Year Trend
+10.5%
Revenue
$2.6 billion
NASDAQ

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