Internship Duration: 6 monthsHours: 40 hours per weekStart Date: Immediately Team Description:We are seeking a highly motivated and detail-oriented intern to join our team to contribute to ongoing ASIC project.
Responsibilities:
- Perform design database management; proper check-in's of golden files, reverting unused changes, merge different files.
- Should be able to code RTL logic with Verfilog syntax.
- Should be able to run simulation using Synopsys VCS.
- Should be able to debug simulation environment; compilation failure, simulation hang, simulation functional failure, etc.
- Should be able to communicate with designers, verification engineers, and other team for the correct solution.
Minimum Qualifications:
- BS/MS degree (completed or in progress) in Electrical Engineering, Electronics, Computer Science, or a related field.
- Must have proficiency in Verilog, SystemVerilog programming language.
- Must have good communication within co-working environments.
- Must have good work ethic, i.e. punctual on deadline, trustworthy commitment on assignment.
- Must be available to work 40 hours per week, Monday - Friday.
- 100% onsite commitment for a 6-month duration.
Preferred Qualifications:- Have a mindset on problem solving.
- Understand ASIC/FPGA workflow from concept to real silicon
- Scripting language skills such as Python, Perl, Tcl, etc.
COMPENSATION: $35/hr - $45/hr 
