Qualifications

• Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or related field.
• Experience in RTL design, functional verification, and/or architecture-level modeling.
• Proficiency with Verilog/SystemVerilog, UVM, and simulation tools (e.g., Synopsys VCS, Cadence Xcelium, Siemens Questa).
• Experience designing and verifying complex subsystems or SoCs, preferably in production or research tapeouts.
• Familiarity with lint, CDC, formal, coverage analysis, and synthesis flows.
• Interest or experience in AI/ML, especially AI-assisted engineering tools, is a major plus.
• Strong collaboration skills and a passion for enabling the next generation of EDA workflows.

Responsibilities

• Collaborate with AI engineers to model and codify chip design and verification workflows.
• Design, implement, and debug RTL designs and SystemVerilog/UVM testbenches used in training and validating AI agents.
• Provide deep domain expertise to help AI agents interpret specifications, generate RTL code, and understand verification coverage.
• Build reusable examples, design patterns, and edge cases to train and evaluate generative and agentic AI models.
• Support benchmarking and evaluation of AI-assisted design and verification productivity across realistic chip development tasks.
• Work closely with customers, product, and research teams to translate engineering pain points into automated AI workflows.

Benefits

• Work at the frontier of AI and semiconductor design.
• Collaborate with a world-class team spanning AI, systems, and EDA.
• Shape a foundational shift in how chips are built.
• Unlimited PTO and full benefits (medical, vision, dental, 401k).
• Two engineering-centric offices with free parking, private gym, and free lunch, drinks and snacks.