Minimum qualifications:- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 8 years of experience with custom silicon design (e.g., SoCs, ASICs, etc.).
- Experience with RTL (Register Transfer Level) design using Verilog or SystemVerilog.
Preferred qualifications:- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience interacting with software, architecture, and other cross-functional teams.
- Experience with a scripting language (e.g., Python or Perl).
- Experience applying engineering best practices (e.g., code review, testing, refactoring).
- Knowledge of processor design, accelerators, or memory hierarchies and machine learning algorithms.
- Knowledge of high performance and low power design techniques.
About the jobIn this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As an ASIC Design Engineer, you will be part of a team developing ASICs used to accelerate computation in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $163000 - $237000 (USD) 15% bonus target bonus equity benefits
Learn more about benefits at Google .
Responsibilities - Contribute to design power modeling and drive convergence to power goals.
- Investigate, specify, and deploy architectural and microarchitectural power optimization techniques.
- Define best practices and methodologies to achieve low-power designs.
- Collaborate with cross-functional software and system teams to create novel power management architectures to meet power goals.
