Minimum qualifications:- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience with verification, SystemVerilog, and UVM.
- 3 years of experience in people management.
Preferred qualifications:- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with universal verification methodology (UVM), SystemVerilog, or other scripting languages such as Python, Perl, Shell, Bash, etc.
- Knowledge of general purpose operating systems such as Linux and Android.
- Familiarity with ARM Instruction Set Architecture.
About the jobIn this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As an ASIC Design Verification Manager for Google's TPU designs, you will lead a team and own the functional verification for key components by guiding the development of advanced infrastructure at the subchip, subsystem, and full-chip levels. This includes developing comprehensive test plans, writing diagnostic codes, and building monitors and checkers to ensure quality assurance.
Additionally, you will partner closely with front-end design, architecture, and performance teams. By analyzing coverage across multiple dimensions, you will help ensure architectural compliance, verify functional correctness, and guide your team to meet key performance goals.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $192000 - $278000 (USD) 20% bonus target equity benefits
Learn more about benefits at Google .
Responsibilities - Guide the functional verification team for portions of TPU designs, setting and communicating individual and team priorities that support organizational goals, providing regular feedback and coaching, and developing functional verification infrastructure across subchip, subsystem, and fullchip level environments.
- Define and guide advanced verification strategies, including the use of simulation, for bug hunt, formal verification for corner-case bugs and emulation for system validation.
- Partner with front-end design, architecture, and performance teams to help ensure architectural compliance and achievement of performance goals.
- Analyze coverage from various dimensions and develop monitors and checkers for quality assurance.
