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ASIC Design Engineer: Top-Tier Opportunities

ASIC Design Engineers are key contributors to the innovative hardware industry, working on microchip and semiconductor designs. …

1,000+ Asic Design Engineer Jobs in Santa Clara, CA

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  • ASIC Design Engineer

    $120K — $150K *Santa Clara, CA (Santa Clara County)In-Person
    Advance innovative memory solutions by researching and developing high-performance architectures. Join our dynamic engineering team to create cutting-edge systems that enhance user experience and transform technology for millions.
    Requirements: Bachelor's Degree, experience in ASIC design and memory architectures.
  • ASIC Design Engineer (eInfochips)

    $120K — $150K *Mountain View, CA (Santa Clara County)In-Person
    Join a team that drives innovative ASIC design, where you'll contribute to high-speed protocol development while leveraging top-tier EDA tools and scripting skills to enhance performance and reliability in cutting-edge technology solutions.
    Requirements: Bachelor's degree, 5+ years in ASIC design, expertise in Fusion Compiler.
  • ASIC Design Engineer

    $120K — $243K *Sunnyvale, CA (Santa Clara County)In-Person
    Join a dynamic silicon group to innovate high-speed ASIC designs and advance the development of cutting-edge networking chips. Collaborate in a supportive environment, enhancing your skills while contributing to world-class technology.
    Requirements: Bachelor's in Electrical Engineering; 3-4+ years ASIC design experience.
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    ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna Labs

    $157K — $212K *Cupertino, CA (Santa Clara County)In-Person
    Contribute to the design and optimization of ASICs for cloud-scale machine learning. Collaborate across teams to deliver high-performance, power-efficient designs, while navigating trade-offs and ensuring design integrity in a fast-paced environment.
    Requirements: Bachelor's degree in EE or related field; ASIC design experience; SystemVerilog.
  • ASIC Design Verification Engineer

    $152K — $219K *San Jose, CA (Santa Clara County)In-Person
    Pioneer the future of ASIC design verification by developing innovative DV infrastructure, executing comprehensive test plans, and collaborating closely across teams to ensure optimal performance and seamless integration of cutting-edge solutions.
    Requirements: Bachelor's + 5 yrs ASIC exp or Master's + 3 yrs or PhD; System Verilog, UVM.
  • ASIC Verification Engineer

    $120K — $160K *San Jose, CA (Santa Clara County)In-Person
    Champion the verification of ARM-based SoCs, leading projects and collaborating cross-functionally. Utilize industry-standard methodologies to ensure top-tier design validation, enhancing performance and security in next-gen technologies.
    Requirements: 8+ years UVM verification exp, BE/BTECH or ME/MTECH in EE/CS, scripting skills.
  • ASIC Design Engineer - Pixel IP DMA

    $120K — $160K *Cupertino, CA (Santa Clara County)In-Person
    Join a team that drives innovation in pixel processing, collaborating across functions to design and validate high-performance DMA engines that enhance product efficiency and power utilization for millions of users.
    Requirements: Bachelor's Degree; experience in multimedia IP/SoC design required.
  • ASIC Design Engineer - Pixel IP DMA

    $130K — $180K *Cupertino, CA (Santa Clara County)In-Person
    Champion innovative Pixel IP design efforts by collaborating across teams to quickly deliver high-performance DMA engines, optimizing data flow for the Pixel IP Engine and impacting millions of customers with cutting-edge technology.
    Requirements: Bachelors + 3 yrs exp in multimedia IP/SoC ASIC RTL design; collaboration skills.
  • SR ASIC Design Engineer - NoC & AXI Interconnect

    $120K — $160K *Santa Clara, CA (Santa Clara County)In-Person
    Drive your career forward by contributing to ASIC design for cutting-edge network chips. Collaborate with cross-functional teams to ensure successful integration and performance in high-impact projects, focusing on innovation and excellence.
    Requirements: Bachelor's/Master's in EE/CE; ASIC design experience; SystemVerilog/Verilog.
  • ASIC Design Engineer lll

    $120K — $243K *Sunnyvale, CA (Santa Clara County)In-Person
    Join a team that's pushing the limits of silicon technology, designing high-speed ASICs to enhance networking solutions. Embrace opportunities for growth and innovation while collaborating in a dynamic, performance-driven environment.
    Requirements: Bachelor's in EE; 4+ years experience; Verilog/System Verilog expertise.
  • ASIC Design Verification Engineering Technical Leader

    $183K — $263K *San Jose, CA (Santa Clara County)In-Person
    Engineer cutting-edge ASIC design verification environments, develop simulation models, and ensure robust testing and coverage in high-end switching products. Collaborate with teams, mentor juniors, and contribute to chip architecture discussions.
    Requirements: Bachelor's or Master's in Electrical/Computer Engineering; 8-10 years ASIC design/verification.
  • ASIC Digital Design, Sr Manager

    $150K — $180K *Sunnyvale, CA (Santa Clara County)In-Person
    Manage and mentor a skilled team in ASIC digital design, focusing on USB architecture and RTL execution. Lead hands-on technical efforts while fostering collaboration and driving high-quality silicon design to meet industry standards.
    Requirements: BSEE/MSEE; 10-12 years in ASIC design; USB expertise; team leadership.
  • ASIC Design Verification Engineer

    $200K — $350K *US-AnywhereRemote in United States
    Drive verification excellence for cutting-edge AI ASICs by developing and executing robust methodologies. Collaborate with design teams while leading the validation process to ensure optimal performance and functionality of innovative silicon solutions.
    Requirements: B.S. in EE/CE, 8+ years ASIC verification, SystemVerilog UVM expertise
  • ASIC/SoC Design Engineer

    $120K — $160K *San Jose, CA (Santa Clara County)In-Person
    Transform complex Adaptive SoC and FPGA design challenges into innovative solutions. Collaborate across teams to drive microarchitectural development and ensure robust configurations in fast-paced environments.
    Requirements: Bachelor's/Master's in Electrical/Computer Engineering; ASIC design experience; Verilog/Systems Verilog expertise.
  • SR ASIC Design Engineer - Networking/ DPU/ AI Systems

    $130K — $180K *Santa Clara, CA (Santa Clara County)In-Person
    Optimize SoC design for advanced AI networking ASICs, driving integration from architecture to silicon bring-up. Collaborate across teams to deliver robust and scalable solutions while owning critical subsystems within a dynamic environment.
    Requirements: Bachelor's/Master's in EE/CE, significant ASIC/SoC experience, RTL design proficiency.
  • SR ASIC Design Engineer - Ethernet Switch & High-Speed I/O

    $120K — $160K *Santa Clara, CA (Santa Clara County)In-Person
    Unlock potential by joining a high-performance ASIC design team focused on cutting-edge network chip development, collaborating closely across teams to ensure first-pass silicon success and delivering innovative solutions in Ethernet design and integration.
    Requirements: Bachelor's/Master's in Computer/Electrical Engineering, skills in RTL design.
  • ASIC Engineering Program Manager

    $210K — $305K *San Jose, CA (Santa Clara County)Hybrid
    Lead cross-functional teams to drive complex ASIC projects from concept to production. Collaborate with engineering, operations, and vendors to ensure quality and efficiency while implementing process improvements in a dynamic environment.
    Requirements: Bachelor's in EE/CE + 12 yrs experience in program management & ASIC development.
  • Sr. Engineer, ASIC Design

    $160K — $192K *San Jose, CA (Santa Clara County)In-Person
    Join a dynamic IC design team and contribute to the design and integration of advanced SoCs. Collaborate on diverse tasks, from RTL design to silicon debugging, while developing your skills in a fast-paced startup environment.
    Requirements: BS/MS in EE/CE, 1+ years in ASIC design, Verilog, ASIC verification tools.
  • Senior ASIC DV Engineer

    $141K — $226K *San Jose, CA (Santa Clara County)In-Person
    Lead the charge in developing complex SOCs for advanced touch and wireless tech. Architect verification environments, validate designs, and refine methodologies to ensure premier product quality and performance in mobile applications.
    Requirements: Bachelor's in engineering, 12+ yrs exp; UVM, mixed-signal skills required.
  • Principal Analog/Mixed-Signal ASIC Engineer

    $258K — $294K *Sunnyvale, CA (Santa Clara County)In-Person
    Transform the future of communication by leading innovation in ASIC designs for advanced electronic and photonic systems. Play a pivotal role in R&D, guiding a dynamic team through the complexities of cutting-edge technology development.
    Requirements: Ph.D. in Electrical Engineering;10+ years ASIC design;high-precision and high-speed expertise.
  • Sr. ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna Labs

    $183K — $247K *Cupertino, CA (Santa Clara County)In-Person
    Deliver cutting-edge hardware designs that optimize performance and efficiency for cloud applications. Collaborate cross-functionally to develop innovative SOC solutions and ensure high-quality results in an environment focused on rapid technological advancement.
    Requirements: Bachelor's in EE; 5+ years RTL/SOC design; VLSI familiarity; Python skills.
  • Architect - FPGA Design, AXI/ UCIe Protocol

    $130K — $180K *Sunnyvale, CA (Santa Clara County)In-Person
    Drive the design and development of cutting-edge Speed Adapter solutions for next-gen protocols, ensuring seamless validation of advanced systems and bridging gaps between hardware and real-world interfaces. Collaborate with teams to revolutionize silicon validation.
    Requirements: 12+ years experience, Bachelor's/Master's in EE/CE, strong RTL skills.
  • Lead Design Engineer

    $114K — $213K *San Jose, CA (Santa Clara County)In-Person
    Lead the charge in pioneering electrical validation for next-gen DDR interfaces, design strategies, and transform data into insight. Collaborate across teams to deliver key reports and provide expert support for customer DDR challenges.
    Requirements: M.Tech + 4 yrs or B.Tech + 6 yrs, expertise in DDR interfaces.
  • Senior FPGA Design Engineer

    $120K — $160K *San Jose, CA (Santa Clara County)In-Person
    Innovate in FPGA design as you engage with cross-functional teams to enhance cloud security solutions and drive state-of-the-art technology integration for complex systems.
    Requirements: BS/MS in EE/EECS/CS; 5+ years FPGA design experience; RTL, Vivado, debugging skills required.
  • Principal Physical Design Engineer, STA

    $209K — $250K *San Jose, CA (Santa Clara County)In-Person
    Lead the charge in timing analysis and sign-off for complex SoCs, collaborating across design and verification teams to ensure robust performance from RTL to sign-off, driving technical excellence in advanced connectivity ASIC development.
    Requirements: BSc in EE/CS; 10+ years STA experience; expertise in physical design tools.
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ASIC Design Engineer

Company Name
$120K — $150K *
Santa Clara, CA 95051
In-Person
Consumer Technology
Less than 5 years of experience
Job Description

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FAQ About Asic Design Engineer Jobs in Santa Clara, CA

What is the typical salary range for an ASIC Design Engineer?

On Ladders, you’ll find ASIC Design Engineer jobs that pay over $100K per year, with many positions offering competitive benefits and opportunities for advancement.

What does an ASIC Design Engineer do?

ASIC Design Engineers are involved in the design and development of application-specific integrated circuits (ASIC). These professionals analyze and refine designs to ensure that systems meet performance and power specifications.

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