Years of Experience
Easy Apply only
As an analog design engineer in the PLL design team, the candidate would be responsible for system-level and circuit-level PLL design. PLL designs will support high-speed Serdes designs such as PCI-Ex...
Develop models for link-level statistical performance simulation of the PHY (Link Training, PHY, DRAM, DB/RCD, DFE training, Transmit Equalization) and application of the same to the development and o...