Minimum qualifications:- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience with silicon implementation and chip integration.
- Experience with STA sign-off constraint authoring for full-chip level, tapeout sign-off requirements, checklists, and associated automation.
- 3 years of experience in people management, developing employees.
- Experience delivering silicon.
Preferred qualifications:- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience in extraction of design parameters, QoR metrics, and analyzing data trends with the knowledge of semiconductor device physics and transistor characteristics.
- Experience in engineering across physical design, top-level implementation, GDS tape-out.
- Ability to deliver silicon in advanced technology process nodes.
- Ability to lead cross-functional teams.
About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
The US base salary range for this full-time position is $192,000-$278,000 bonus equity benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .
Responsibilities- Lead and manage functional Static Timing Analysis (STA) team responsible for delivering system-on-chip (SoC) STA.
- Execute full chip timing sign-off checklist, perform full chip STA, power recovery, timing ECO creation and oversee final timing sign-off for SoC's.
- Define SoC timing sign-off process corners, derates, uncertainties and their trade-offs.
- Drive clock tree planning and implementation for SoCs to achieve best energy, performance and area.
- Collaborate with front-end, Design for Test (DFT) and Computer-aided design (CAD) teams for the design exploration and closure.
