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X Applicants in San Francisco: Qualified applications with arrest or conviction records will be considered for employment in accordance with the San Francisco Fair Chance Ordinance for Employers and the California Fair Chance Act.Note: By applying to this position you will have an opportunity to share your preferred working location from the following:
New York, NY, USA; Zürich, Switzerland; Mountain View, CA, USA; San Francisco, CA, USA.
Minimum qualifications: - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 10 years of experience with leading multiple design domains (Design For Test, Design Verification and Physical Design).
- 5 years of experience with logic design, computer architecture, and circuit theory.
- 5 years of experience in power or performance modeling or system performance analysis.
Preferred qualifications: - Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- 2 year of experience in linux kernel programming.
- Experience with processor core architectures (such as ARM, x86, RISC-V, etc.) and IPs commonly used in SoC designs.
About the jobAs a part of today's hyperscale AI competition, accelerators have become a strategic differentiator. In this role, you will help deliver codesigned systems that, unlike classic data center infrastructure, must meet future demands as our workloads continue to evolve and mutate. You will deploying new hardware in Google data centers through our projects to drive enhanced capabilities and efficiency, partner closely with the teams responsible for Google's technical infrastructure to successfully deliver these systems.
In this role, you will join a co-design team within DeepMind's GenAI Systems, operating across Google's vertically integrated stack. In this role, you will bring expertise spanning hardware, including architecture, logic design, design verification, and physical design software, such as compilation, performance optimization, libraries, operating systems, and kernels, and algorithms, covering ML model design, optimization methods, numerics, and sparsity. In these fields, you will conduct cutting-edge research while delivering production-quality hardware and software products.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $256000 - $278000 (USD) 20% bonus target
Learn more about benefits at Google .
Responsibilities - Architect, design, and implement hardware for novel systolic array accelerators.
- Own subsystems up to the entire accelerator, carry the implementation of those subsystems from requirements through design sketches, implementation, timing closure, through tapeout, and into bringup and application mapping.
- Collaborate with application, algorithm, and performance-tuning experts to codesign solutions for the best efficiency, performance, and programmability.
- Write code for accelerators to meet up with production requirements at the system, library, and application levels.
- Bring a generalist approach to computer systems beyond specific hardware-related skills, interfacing with colleagues in a wide span of disciplines.
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