Minimum qualifications:- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience with physical design flow and methodologies.
- Experience with EDA tools for physical design (e.g., Cadence, Synopsys, Siemens).
- Experience in full-chip or block-level physical design.
- Experience with scripting in Python, Tcl, or Perl.
Preferred qualifications:- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- 12 years of experience in physical design flow and methodologies for high-performance ASIC/SoC projects.
- Experience in sign-off areas such as physical verification (Caliber/IC Validator), Formal Verification (LEC), extraction, low power verification, STA closure, and ECO flows.
- Experience in achieving optimal Power, Performance, Area (PPA) goals in complex designs.
- Ability to develop and deploy repeatable design methodologies, focusing on low-power verification.
- Familiarity with 2.5D/3D IC packaging and proficiency with advanced parasitic extraction tools (e.g., STARRC).
About the jobIn this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Join the Chip Innovation Infrastructure team to engineer the future of ASIC design at Google. You will own the development of cutting-edge flows, methodologies, and data management systems for physical design EDA tools operating within the Google Compute Engine environment. This role is a core catalyst: you will survey industry trends, perform technical evaluations, and implement best practices to streamline RTL-to-GDS workflows, dramatically increasing the efficiency of our physical design engineers and ensuring the high quality of results for all ASIC tapeouts. You will have deep experience with industry-standard physical design tools and a solid command of common scripting languages.
US: $192000 - $279000 (USD) 20% bonus target equity benefits
Learn more about benefits at Google .
Responsibilities- Architect and implement next generation Physical Design EDA CAD tool workflows for ASIC development.
- Collaborate with chip design teams to implement tools and methodologies for physical design in leading edge process nodes.
- Develop auditing tools, checkers, and metric dashboards based on APIs from third-party EDA tools.
- Own the physical design of blocks and subsystems end-to-end.
