We are seeking Digital Design Verification Engineers to verify our custom ASICs for satellite and wireless telephony. Knowing Verilog, SystemVerilog, and UVM is a must, VHDL is valuable. We prioritize AI assistance to accelerate work. Requirements • Strong proficiency in Verilog and SystemVerilog • Experience writing tests within an existing UVM verification environment • Solid understanding of UVM architecture and methodology • Ability to write C/C++ code for verification purposes • Some scripting experience in Perl or Python • Ability to contribute to and help write test plans • Experience writing and maintaining verification tests • Ability to debug RTL simulations independently • Experience leading design verification efforts at the block level • Experience driving code coverage closure on assigned blocks What you bring to this role: • 6+ years of design verification experience in the semiconductor industry This is a full time, exempt position, based out of our Saratoga office. The target base pay for this position is $120,000 - $220,000 annually. The total compensation packaged will be determined by various factors such as your relevant job-related knowledge, skills, and experience. We are redefining how satellites are designed, manufactured and used-so we're looking for candidates with passion, deep knowledge and direct experience on LEO satellite component development, design and in-orbit activities. If that's your experience - then we'll be immediately wow-ed. E-Space is not currently able to provide employment sponsorship for candidates who do not hold work authorization for the location of this role.