Your Team, Your Impact
The Connectivity BU develops cutting-edge optical Ethernet Transceiver ASICs.

The latest datacenter architectures need to scale rapidly for widescale AI adoption. In order to respond to the dramatically increased demands of cloud-based connection capability, major hyperscalers urgently demand faster and more secure internet connection components. One critical part of that component includes the optical ethernet transceiver ASICs. As a member of a digital hardware development team, the candidate will be assisting in chip design, verification, supporting back-end teams and timing closure.

This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. The customers served by this team are often other chip companies and big tech companies, familiar names to all candidates.

What You Can Expect

What You Can Expect

• Participate in various aspects of chip design RTL development, synthesis, static timing analysis, formal equivalence, RTL lint, cross clock domain (CDC) analysis and functional verification.
• Develop high speed data path and control plane RTL blocks using Verilog, synthesis and backend resources
• Integrate vendor IP and support
• Well versed with the complete ASIC flow from micro-architecture to customer deployment
• Post-silicon debug and correlation
• Develop ASIC specification and micro-architecture of signal processing and communications algorithms
• Assist in design automation of various aspects of the CAD EDA flow.

What We're Looking For

hat We're Looking For

• Bachelor's degree in Computer Science, Electrical Engineering or related fields and 5+ years of related professional experience. OR Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3+ years of experience.
• 5+ years of experience (or equivalent) in multi-million gates digital/mixed-signal IC design at 16nm or smaller technology.
• Familiarity with the entire design cycle from micro-architecture specification definition, verilog coding, synthesis and timing closure to post-silicon debug and support in lab environment.
• Experience with Verilog, System Verilog, Python, and Unix Shell.
• Experience in both RTL development (block and subsystem level) and gate level verification and debug.
• Ability to multi-task and must be flexible and adaptable to a rapidly changing and demanding environment
• Effective communication and presentation skills and a team player

Expected Base Pay Range (CAD)
98,100 - 130,800, $ per annum

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We're dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it's like to work at Marvell, visit our Careers page.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

Marvell may employ artificial intelligence technologies to assist in the evaluation of job applications. All application reviews include meaningful human involvement, and no hiring decisions are made solely on the basis of automated processing.

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