Advanced Micro Devices, Inc

STA/Constraints Engineer

Advanced Micro Devices, Inc • $110K — $130K *
Vancouver, BC V5K 5J9In-Person
Information Technology
Less than 5 years of experience
Today
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Job Overview by Ladders

Qualifications

  • 5-7 years of industry experience in STA and timing signoff.
  • Expertise with industry-standard PD tools like SNPS PT/GCA; ICC2/FC knowledge is a plus.
  • Proficiency in scripting languages such as Perl, TCL, Shell, and Python.
  • Experience with Verilog RTL design in large digital ASIC projects.
  • Strong communication skills, both written and verbal.
  • Experience with lower power design methodology is advantageous.
  • A Bachelor's or Master's degree in Micro Electronics, Integrated Circuit Science, or a related field.

Responsibilities

  • Own the end-to-end delivery of designs, focusing on timing constraints and signoff.
  • Collaborate with the SOC Architecture team on clocks and statistical timing goals.
  • Set up clock design requirements in SDC accurately.
  • Analyze timing margins on advanced tech nodes, collaborating with methodology teams.
  • Ensure timely delivery of FCT closure based on project requirements.
  • Work with CAD and EDA vendors to enhance timing closure methodologies.
  • Oversee timing closure and quality checks with RTL designers and physical design teams.

Benefits

  • Comprehensive AMD benefits package available.
  • Hybrid work arrangement in Vancouver, BC.
  • Opportunities for professional growth and mentoring.
Full Job Description

THE ROLE: 

The STA/Constraints Engineer is responsible for developing FullChip constraints and timing closure. Person will work closely with Fellows, Principal Engineers, Architects, collaborate with cross functional worldwide teams across Physical Design, Timing Analysis, Synthesis, Physical Verification, Power signoff, and mentor/coach/guide Design Engineers.

 

KEY RESPONSIBILITIES:  

 

  • Own end-to-end delivery of designs (SOC and Sub-system integration) from timing constraints and timing signoff perspective.
  • Work closely with the SOC Architecture team for SOC clocks & STA for statistical timing target goals.
  • Understanding clock design requirements and making sure they are correctly set up in SDC.
  • Understand timing margins (LVF/SSTA/Variations etc.) on the latest tech nodes and work with timing methodology teams for future and current projects.
  • Understand design requirements, timelines and various milestones of a project and deliver FCT closure accordingly.
  • Collaborate with CAD and EDA vendors to further strengthen AMD timing closure and constraints methodology.
  • Responsible for cdc/lint, timing closure, lower power implementation and netlist quality check with RTL designer and PD team.
  • Work on SDC development, STA (Static Timing)  analysis, shift left of timing closure, CDC (Clock Domain Crossing).

PREFERRED EXPERIENCE:  

  • Industry experience in STA, constraints and timing signoff.
  • Expert user of industry-standard PD tools like SNPS PT/GCA (must) and ICC2/FC (desired). 
  • Good experience with Perl/TCL/Shell/Python scripting, and Verilog RTL design.
  • Excellent presentation and inter-communication skills.
  • Experience with Verilog RTL design/implementation and has experience of large digital ASIC project.
  • Experience with physical design is a plus.
  • Has Synthesis or physical implement experience.
  • Experience with lower power design methodology.
  • Good English skills on talking, presentation and writing documents.
  • Good communication and strong sense of responsibility, task scheduling, and time management.

ACADEMIC CREDENTIALS:  

  • Bachelor/Master’s degree in Micro Electronics/ Integrated Circuit Science, or related field preferred.

LOCATION: Vancouver, BC

 

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Benefits offered are described:  AMD benefits at a glance.

 

About Advanced Micro Devices, Inc

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Learn more about Advanced Micro Devices, Inc
Size
15,500 employees
Market Cap
$100.9 billion
Industry
Manufacturing & Automotive
Net Income
$2.4 billion
Founded
1969
5 Year Trend
+30.9%
Revenue
$9.7 billion
NASDAQ
AMD
* Ladders Estimates

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