Title: Principal Engineer - IO/Interface IP lead
Summary of Role: We are seeking a Principal Engineer with deep expertise in I/O and interface designs.
Essential Responsibilities: - Lead I/O and interface design for automotive and industrial CPU/IP/Custom SOC products. Define and execute I/O's including selection, design and integration into different SoC platforms. Good understanding of various interface communication protocols such as GPIO, I2C/I3C, DDR, CAN, Ethernet, LVDS, MIPI, USB, PCIe etc.
- Interface Design leadership with deeper understanding of overall system level interface requirements covering performance, timing, timing budgeting, signal integrity and power requirements
- Cross-collaboration and system level leadership working closely with different disciplines such as SoC Design, Board/System level design, and customers to develop compelling and differentiated solutions. Strong understanding of system level issues such as power sequencing, reliability considerations and proven low-power design expertise addressing markets across portable/mobile, Industrial and Automotive
- Define and drive interface specifications for stand-alone IP and SoCs across different applications. Create interface requirement and integration requirements. Define and contribute to datasheets and reference manuals
- Driving roadmap, innovation to address trends in interface standards. Address technology node gaps with innovative circuit design techniques, working closely with design team/foundry team in influencing component and product level roadmaps. Drive a culture of strong innovation across power, performance, area and reliability
- Validation and Characterization skills on post-silicon. Ability to define validation and characterization requirements. Understanding interface compliance requirement needs and drive validation teams. Define architecture to meet Design For Test (DFT) requirements and document bring-up, initialization procedures
- Mentorship and leadership in providing technical guidance and mentorship to other junior engineers working on interface subsystems. Providing technical guidance across teams on topics related to I/O interfaces
- Customer and partner support leadership to address technical queries, support, and resolve issues related to I/O interfaces
- Stay current with the latest trends in semiconductor design, and latest I/O and interface IP innovations, providing technical leadership and mentoring within the Hardware engineering team
Other Responsibilities:Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.
Required Qualifications:- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Minimum 15+ years of experience in I/O design, interface standards covering both design and layout. Proven expertise in advanced technology nodes is required
- Deep understanding of interface standards and design covering both high-speed and low-speed, low-power designs. Experience in ESD, high voltage design and proven record of meeting power, performance and area requirements.
- Hands-on experience in understanding trade-offs and design understanding of signal/power integrity constraints, package/PCB design, firmware interaction with I/O subsystems
- Working knowledge and understanding of industry-standard EDA tools for design and simulation such as Cadence, Synopsys, Keysight, Ansys etc.
- Strong analytical and debugging skills: Ability to identify, assess, and aid in debugging complex problems. Familiarity with lab equipment is highly desirable
- Excellent communication and documentation skills: Capable of producing clear, comprehensive requirements and architecture documentation for both internal and external usage
- Collaborative mindset: Comfortable working in global, cross-disciplinary teams and engaging directly with customers and partners
Preferred Qualifications:- Experience in ISO 26262/IEC 61508: Experience in applying the standard throughout the development lifecycle, especially at the semiconductor IP and SoC level.
- Contributions to interface standards such JEDEC, MIPI or other board standards such as SGET etc.
Expected Salary Range$171,000.00 - $296,000.00
The exact Salary will be determined based on qualifications, experience and location.
