Job Role and Responsibility: AMD, Inc., is hiring Sr. Manager Silicon Design Engineering to Develop and establish timing closure methodologies and strategies for SoC and IP blocks to ensure compliance with requirements and provide technical guidance to execution teams. Oversee STA closure for complex SoC designs featuring chiplet and 3D stack interfaces. Leverage extensive knowledge and experience in physical design and full-chip timing to tackle large, cutting-edge designs, ensuring high-quality, on time delivery. Understand the SoC as an integrated system while optimizing for performance and power. Collaborate cross-functionally with IP, Domain, CAD, and Methodology teams to identify and address intricate technical challenges and risks, and create solutions to meet product specifications. Share knowledge and contribute to various SoC functions. As the overall STA and clocking lead, take responsibility for architectural analysis and the scoping/assessment of feature changes. Partner closely with design teams to refine clocking, area and floorplan, set timing targets, and secure performance sign-offs. Assist Post-Silicon teams with debugging and resolving timing issues. Utilize knowledge of computers and electronics, including circuit boards, processors, chips, and electronic equipment, as well as knowledge of design techniques, tools, and principles. Apply knowledge of engineering principles, best practices, and technologies to the design, development, and testing of various company proprietary products.
Can work remotely.
Supervises.
Multiple openings. Qualified applicants click
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Travel required: NO
Qualifications: Degree requiredMaster's degree or foreign equivalent in Electronics Engineering, Computer Science, Computer Engineering, or Electrical Engineering or related field.
Qualifications: Amount and type of experience required: Four (4) years of experience in the job offered or a closely related engineering role.
Alternate combination of education and experience: Employer will alternatively accept a Bachelor's degree or foreign equivalent in Electronics Engineering, Computer Science, Computer Engineering, or Electrical Engineering or related field and six (6) years of experience in the job offered or a closely related engineering role.
Specific skills required: The following skills are required:Position requires four (4) years of experience in the following:
- Using Computer-Aided Design (CAD) tools to oversee the entire chip design process;
- Overseeing the physical design of deep submicron digital ASICs;
- ASIC design tools, including synthesis, simulation, equivalence checking, and static timing analysis;
- Using back-end Electronic Design Automation (EDA) tools to oversee the physical implementation of a chip design;
- Scripting in TCL, Perl or Python to automate repetitive steps in the design process, such as logic synthesis, timing analysis, or place-and-route;
- Overseeing Static Timing Analysis (STA) closure to ensure a chip design will function correctly at its target speed;
- Owning global clock tree construction and analysis for best PPA;
- Using Physical Design Closure, including floor planning, placement, clock tree synthesis (CTS), routing, and timing closure;
- Managing silicon design projects; and
- Leading an engineering team.
Can work remotelySupervisesPreferred Skills: N/A#LI-AM4
Benefits offered are described: AMD benefits at a glance.
