Sr. Engineer, ASIC Design

Ayar Labs

$160K — $192K *
Telecommunications & Hardware
Less than 5 years of experience
Job Overview by Ladders

Qualifications

  • BS or MS in Electrical Engineering, Computer Engineering, or related fields
  • 1+ years of work or academic experience in ASIC design
  • History of independently managing diverse technical tasks
  • Proficient in Verilog for RTL design and verification
  • Proficient in ASIC verification tools like XCelium, VCS, Questa
  • Proficient in scripting or programming languages

Responsibilities

  • Develop and optimize RTL designs for complex digital systems
  • Create verification methodologies and testbenches for digital and mixed-signal blocks
  • Bring up, evaluate, and debug in-house custom silicon using Python scripting and firmware
  • Document designs for backend ASIC engineers to ensure proper physical implementation
  • Collaborate with team members to ensure timing signoff

Benefits

  • Work in a dynamic startup environment
  • Opportunities for professional growth and skill development
  • Collaborative and supportive small team atmosphere
Full Job Description
Engineer, ASIC Design

Location: San Jose (on-site)

The ASIC Engineer is responsible for design and integration of complex SoCs with both high-speed custom and digital blocks. You will work in a dynamic startup environment as part of a small IC design team, covering roles from custom circuit design to optical device design. Each team member is expected to contribute across a broad range of tasks and to gain new skill sets to grow with the company. The ideal candidate is a hands-on self-starter who can craft specifications based on input from colleagues, customers, and industry and who can effectively manage his or her own time to take projects to completion with limited supervision and guidance.

KEY RESPONSIBILITIES:
  • Develop and optimize RTL designs for use in complex digital systems
  • Develop verification methodology and testbenches for digital and mixed-signal blocks
  • Bringup, evaluation, and debug of in-house custom silicon using python scripting, firmware, and control systems
  • Create clear documentation of their designs to enable backend ASIC engineers to perform physical implementation (clocks and timing constraints, floorplan guidance, testability) and collaborate to ensure timing signoff


Required Skills:
  • BS or MS in Electrical Engineering, Computer Engineering, or related fields
  • 1+ years of work or academic experience in ASIC design
  • History of assuming responsibility for a variety of technical tasks and completing projects independently
  • Proficient in Verilog for both RTL design and verification
  • Proficient in ASIC verification (XCelium, VCS, Questa) tools
  • Proficient in scripting or programming languages


Preferred Skills:
  • Proficient in writing timing constraints and deep understanding of timing analysis
  • Experience working on digital designs with multiple clock domains and clock dividers
  • Working knowledge integrating custom blocks in a digital-top flow (LEF, lib, etc.)
  • Performed silicon bring-up, debug, and evaluation
  • Programming experience in Python, low-level languages (C, C++)
  • Some knowledge of optics and control systems


Salary Range: $160,000 - $192,000

NOTE TO RECRUITERS:
Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don't send candidates to Ayar Labs, and do not contact our managers.

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