Minimum qualifications:- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 5 years of experience in high-performance ASIC design.
- Experience architecting or designing RTL solutions for digital systems.
- Experience with high-speed interconnects.
- Experience developing networking IP across one or more layers, such as the media access control (MAC), link (L2), or physical (PHY) layers.
Preferred qualifications:- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- 7 years of experience in high-performance ASIC design.
- Experience with IEEE networking standards and applications.
- Experience with scripting languages (e.g., Tcl, Python or Perl).
- Familiarity with one or more industry-standard tools for CDC, RDC, RTL Linting, or LEC.
- Understanding of digital design fundamentals, including synchronous and asynchronous logic, state machines, and bus protocols.
About the jobIn this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Join the team designing and developing the core components of Google's next-generation Tensor Processing Units (TPUs), the custom-built accelerators powering our AI and machine learning workloads in data centers.
As a member of the inter-chip interconnect team, you will play an important role in designing ASIC/SoC hardware for AI and networking accelerators that drive the computational workloads behind Google's most important products. Our hardware accelerators power nearly every product Google offers. Our primary focus is AI acceleration.
You will design register-transfer level (RTL) IP with a focus on chip-to-chip high-speed interconnect subsystems. You will have dynamic, multi-faceted responsibilities in areas such as project definition, RTL design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators. You will have the opportunity to solve challenging technical problems at the forefront of AI hardware, working in a dynamic and collaborative environment.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training. $163000 - $237000 (USD) 15% bonus target bonus equity benefits Learn more about benefits at Google .
Responsibilities - Lead the microarchitecture and RTL execution to deliver high-performance network design components which meet strict power, performance and area (PPA) goals and satisfy established coding and quality guidelines.
- Collaborate with system architects and software/firmaware teams to ensure alignment between system and IP requirements.
- Own the complete RTL lifecycle from initial microarchitecture, coding and documentation to ensuring sign-off readiness for Lint, CDC, and synthesis.
- Collaborate with the Verification team to develop test plans, debug RTL, and ensure functional correctness.
- Work closely with the Physical Design team to meet timing, area, power, and manufacturability requirements.
