Sr Design Verification Engineer (Remote)
Full-time: Salary + Benefits + Bonuses / Contractor
Work Status: US citizen or Lawful Permanent Resident.
Location: Irvine CA
Digital ASIC Verification Engineer
We are looking for an experienced Digital ASIC Verification Engineer to verify complex digital systems, including ARM-based CPUs and DSP blocks. You will own the full verification lifecycle, from test planning to coverage closure using SystemVerilog and UVM.
Responsibilities
- Develop UVM/SystemVerilog testbenches for block and system-level verification
- Create and execute test plans; drive functional and code coverage closure
- Automate test generation and regressions using Python and MATLAB
- Support pre-silicon verification and post-silicon bring-up
- Collaborate across teams to ensure design quality and integrity
Qualifications
- 10+ years of ASIC verification experience
- Strong skills in SystemVerilog, UVM, and constrained random verification
- Familiarity with ARM/CPU architecture and OOP concepts
- Proficiency in Python scripting (MATLAB a plus)
- Bachelors in EE/CS/CE (Master's preferred)
The anticipated annual base salary for this position is between $150,000 to $165,000, which also includes a comprehensive benefits package.
Full-Time Benefits: • 15 days of PTO per calendar year
• 10 paid Holidays per calendar year
• Comprehensive Medical Benefits: Company covers 80% of premiums for Employee and Dependents
• Dental & Vision: Company covers 50% of premiums for Employee and Dependents
• Voluntary Benefits: Life Insurance, FSA (Health and Dependent, Limited Purpose), HAS, and Gap Insurance
• Employee Assistant Program (EAP)
• 401k - Traditional & Roth
• Life/AD&D and Long-Term Disability
• Tuition reimbursement
LinkedIn :: https://www.linkedin.com/in/rtl2gds/
