OverviewThecandidate will be part ofRambus Memory Interface Chips BUs design group responsible forspecifying, architecting, executing, and productizing leading edgememory interface buffer chipsfor DDR5, DDR6 and beyond.
Responsibilities
- Ownerand domain expertof analog and mixed signaldesigns at chip and block level, especially for high-speed data receivers
- Architect, design, simulate and characterize high-performance and low-power high-speedcircuits including receiver, samplers, and signal conditioning circuits
- Modeling ofchip and block levelat various levels of detail for design tradeoff analysis and voltage and timing budgeting
- Superviseanalog layoutengineeringto ensure attention to detailon high performance analog layout for critical IO blocks
- Work closely with cross-functional teams across different geographies and time zones to ensure engagement and execution
- Other responsibilities include layout supervision,designdocumentation, guiding and debugging post-silicon validation, correlating silicon to simulation
Qualifications
- MSEE/Ph.D. with10+ years of analog / mixed-signal circuit design experience
- Must have understanding of SI/PI principles and interaction with receiver front-end principles
- Direct chip design experience in DDR interface design is a strong plus
- Experience with Verilog coding is a strong plus
- Must be a team player with good written and verbal communication skills, self-motivated, thorough design styles, detail oriented, and work with multiple functional teams with good engineering practices.
Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program, and gym membership.
The US salary range for this full-time position is $169,400 to $254,000. Our salary ranges are determined by role, level and location. The successful candidates starting pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.
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