OverviewAs aSenior Principal Architect of Memory & IO Sub-system,youll play a pivotal role inleading the architecture, design, and development of next generation ofDRAMsub-system solutionsfor server andhigh-performancecomputing applications. In thisfull-timerole, youll report directly to ourVP of Engineering. OurMemory Interface Divisionis dedicated todevelopingallproductsrelated toServer and Client Memory Modules, and your contributions will be instrumental indevelopingsolutions DDR6/LPDDR6/HBM solutions for Server and Clientsystems.
Rambus offers a flexible work environment, embracinga hybrid approach formostoffice-basedroles.Employeesare encouragedtospend an average of at leastthree days per weekonsite,allowing fortwodaysof remote work.
Responsibilities
Lechnical Leadership
- Lead the architecture, design, and development of next generation of memory subsystem solutions.
- Drive technical decisions related to memory interfaces, PHY architecture, signal & power integrity, and system integration.
- Define subsystem requirements and translate system-level needs into architecture and design specifications.
- Provide technical leadership across multidisciplinary teams including ASIC, PHY, firmware, validation, system architecture, and platform engineering.
Memory Subsystem Development
- Develop expertise-driven solutions involving:
- DDR4/5/6, LPDDR4/5/6, HBM3/4/5 DRAM
- DDR4/5/6 Registered Clock Driver (RCD)
- DDR4/5/6 Data Buffer (DB)
- DDR4/5/6 DIMMs (RDIMM/LRDIMM/MRDIMM)
- DDR4/5/6 Server Platforms
- Analyze memory subsystem performance, timing, power, and interoperability requirements.
- Drivesystemsbring-up, debug, characterization, and performance optimization activities.
PHY Architecture and Design
- Define and review high-speed PHY architectures for next-generation memory and interface products.
- Transmitter (Tx) architectures
- Receiver (Rx) architectures
- Clocking and timing circuits
- Equalization schemes including DFE, CTLE, and related signal-conditioning techniques
- Evaluate signal integrity challenges and develop solutions to improve channel performance and margin.
Digital Design and Verification
- Contribute to digital design, architecture reviews, and RTL implementation strategies.
- Define verification methodologies and coverage requirements.
- Lead debugging and root-cause analysis of complex design and system-level issues.
- Collaborate with validation teams to ensure robust product functionality and compliance.
Specification and Customer Engagement
- Develop and maintain architecture specifications, design requirements, and technical documentation.
- Present technical proposals, design reviews, and architecture recommendations to engineering leadership, customers, and ecosystem partners.
- Translate JEDEC and industry standards into product requirements and implementation guidelines.
- Participate in customer discussions, technical reviews, and interoperability initiatives.
Qualifications
Education
- Masters Degree (M.S.) in Electrical Engineering, Computer Engineering, or a related technical discipline.
Experience
- 12+ years of industry experience in semiconductor, ASIC, memory, or high-speed interface development.
- Demonstrated experience leading complex technical projects and influencing architectural decisions.
Key Competencies
- System Architecture Leadership
- DDR5/DDR6/LPDDR5/HBM Memory Expertise
- Tx/Rx Circuit Architecture
- DFE/CTLE Equalization Techniques
- Digital Design & Verification
- Technical Specification Development
- Analytical Problem Solving
- Executive-Level Presentations
Rambus offers a competitive compensation packageincludingbase salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program, and gym membership.
TheUSsalary range for thisfull-timeposition is $180,000to $334,200.Our salary ranges aredeterminedby role,leveland location. The successful candidates starting pay will bedeterminedbased on job-related skills, experience, qualifications, worklocationand market conditions.
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