Cadence Design Systems

Solutions Engineer - AE

Cadence Design Systems • $100K — $130K *
Austin, TX 78745In-Person
Consumer Technology
Less than 5 years of experience
Today
Be an Early Applicant
Job Overview by Ladders

Qualifications

  • Master's degree in Electrical Engineering, Computer Engineering, or related field
  • Minimum one year of relevant engineering experience
  • Expertise in standard cell library characterization
  • Knowledge of standard cell library design focusing on PPA optimization
  • Proficient with Cadence Virtuoso tool suite and Liberate for standard cell characterization
  • Experience with foundation IP library characterization
  • Ability to perform library comparisons across different PDKs

Responsibilities

  • Research, design, and develop electronic components for EDA and semiconductor IP
  • Engage with customers on library development methodologies and views generation
  • Scope effort, perform library characterization, and generate logical and physical views
  • Support customer adoption and drive business for Cadence library development tools
  • Collaborate with R&D on improving tools and methodologies
  • Create technical content for Cadence online support
  • Execute digital place and route tasks as needed

Benefits

  • Some telecommuting permitted
  • Opportunity to work with cutting-edge technology in EDA
  • Collaborative work environment with R&D
  • Engagement with a diverse range of clients
  • Professional growth through customer-facing experience and technical writing contributions
Full Job Description
Job Duties:

  • Research, design, develop, and test electronic components and systems for Electronic Design Automation (EDA) and semiconductor intellectual property (IP) employing knowledge of electronic theory and materials properties.
  • Interface with customers regarding library development methodologies, including timing characterization, EMIR view generation, physical view generation (LEF (Library Exchange Format), GDS (Graphic Data System), abstracts, etc.), logical view generation (LIB (Liberty), CDL (Circuit Description Language), Spectre, etc.), and technology LEF creation for digital tools.
  • Scope the level of effort, perform library characterization, generate logical and physical views such as PGV (Power Grid View), Verilog, LEF, DSPF (Detailed Standard Parasitic Format), etc., and support validation of the results.
  • Support adoption and proliferation of existing customers (on/offsite) to help drive business for Cadence library development tools.
  • Work closely with Research and Development (R&D) on tools and methodology improvements.
  • Create and contribute technical content for Cadence online support.
  • Perform other digital place and route (P&R) tasks as needed by the group.
  • Some telecommuting permitted.


Qualifications:

  • Master's degree in Electrical Engineering, Computer Engineering, or related field.
  • Minimum one (1) year of experience in the job offered or in a related engineering occupation.
  • Standard cell library characterization
  • Standard cell library design knowledge, specifically standard cell development to optimize PPA using Cadence characterization tools
  • Utilize Cadence Virtuoso tool Suite and Liberate to standard cell characterization for PPA analysis and optimization for tools and library
  • Characterization of foundation IP library
  • Library comparison and analysis across Process Design Kit (PDK) and foundry

About Cadence Design Systems

Cadence Design Systems, Inc. is an American multinational electronic design automation software and engineering services company, founded in 1988 by the merger of SDA Systems and ECAD, Inc. The company produces software, hardware and silicon structures for designing integrated circuits, systems on chips (SoCs) and printed circuit boards.
Learn more about Cadence Design Systems
Size
9,300 employees
Market Cap
$43.9 billion
Industry
Enterprise Technology
Net Income
$590.6 million
Founded
2018
5 Year Trend
+10.5%
Revenue
$2.6 billion
NASDAQ
CDNS
* Ladders Estimates

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