About the RoleYou will build the low-level device runtime that turns compiled programs into efficient, functional and performant execution on OpenAI's custom AI accelerator. This software will schedule kernel launches, manage device memory and address spaces, coordinate synchronization, and expose reliable abstractions to higher-level runtimes and frameworks.
You will work at the boundary of software and hardware, partnering with compiler, kernel, architecture, verification, and silicon teams to define interfaces and validate behavior. You will also use and improve event-based, cycle-accurate simulation to develop runtime capabilities before silicon is available, diagnose performance and correctness issues, and guide hardware-software co-design.
In this role, you will:- Design and implement the low-level device runtime for OpenAI custom silicon.
- Build kernel-launch scheduling, command submission, queueing, dependency tracking, and completion handling.
- Manage device memory spaces, allocation, virtual-to-physical mappings, data movement, and lifetime across concurrent workloads.
- Implement synchronization primitives, events, barriers, streams, and ordering guarantees that are correct and efficient.
- Define clean interfaces between the runtime, drivers, firmware, compiler-generated code, kernels, and higher-level execution systems.
- Use event-based, cycle-accurate simulators to develop, validate, debug, and performance-tune runtime behavior before and after silicon availability.
- Diagnose concurrency, memory-ordering, deadlock, race, correctness, and performance issues across software and hardware boundaries.
- Build tests, tracing, profiling, observability, and reproducible workloads for runtime correctness and performance.
- Partner with architecture and silicon teams to turn workload and simulator insights into hardware-software interface improvements.
You might thrive in this role if you:- Have strong low-level systems programming experience in C, C++, Rust, or comparable environments.
- Have built runtimes, drivers, firmware, operating-system components, accelerator software, or adjacent systems infrastructure.
- Understand concurrency, synchronization, asynchronous execution, queues, events, and memory-ordering semantics.
- Understand memory management, address spaces, DMA, caching, coherency, and hardware-software interfaces.
- Have hands-on experience with event-based, cycle-accurate simulators or closely related architectural and performance models.
- Can reason quantitatively about scheduling, latency, throughput, utilization, contention, and resource tradeoffs.
- Are skilled at debugging failures that span software abstractions, device interfaces, and hardware behavior.
- Work effectively across compiler, kernel, architecture, verification, firmware, and silicon teams.
To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations.
