Minimum qualifications:- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 4 years of experience in two or more of the following areas: computer architecture, embedded firmware, ASIC design or verification, or integration and enablement of first- or third-party IP.
- Experience in hardware and software integration or validation.
- Experience with RTL development, design verification, or evaluation.
Preferred qualifications:- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with C /Python software design principles.
- Experience integrating complex hardware/software systems.
- Experience developing firmware for embedded systems or accelerators.
- Proficiency in debugging firmware using simulation tools and/or working knowledge of RTOS internals.
About the jobIn this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, you will be working on cutting-edge ASIC development, validation, software, tools, and methodologies and have the ability to push the boundaries of chip-development and hardware/software integration and validation.
Own cross-functional work streams focused on hardware/software (HW/SW) integration and validation to demonstrate HW, SW, and system functionality and performance. Help the chip team accomplish key silicon development criteria, meet chip and system schedules and achieve readiness for production in various silicon and system validation environments. Serve as a key bridge between specification, design, and verification teams as well as compiler and performance teams with technical depth and breadth across the ML compute IP.
You may write firmware, RTL, scripts, or test content to integrate and demonstrate subsystem and system functionality. You will validate this functionality on simulation, emulation, or post-silicon environments.
You will support demonstrating and delivering that complex hardware and software systems are functional and performant. You will support the coordination, debug, and ennoblement of the platform.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $138000 - $198000 (USD) 15% bonus target equity benefits
Learn more about benefits at Google .
Responsibilities - Review chip spec and design, develop the integration plan with SW and System partners, coordinate HW and SW delivery and demonstrate functionality.
- Assist bringup of ML Compute features. Integrate and validate complex hardware and software designs, including first- and third-party IPs. Develop firmware to help validate hardware functionality.
- Utilize HW-SW co-simulation methodologies leveraging RTL simulation, Emulation, FPGA environments as appropriate. Leverage architectural simulators or performance models as required to correlate performance.
- Develop detailed test plans, based on design specifications coordinated with a cross-functional team (e.g. design, DV, firmware, compiler, architecture).
- Assist debug discussions with Design/DV/SW/Architecture teams and help root-cause functional failures and performance issues through the product development cycle. Improve validation coverage and sign-off processes for high-quality tapeout and production deployment.
