The Silicon Physical Design team is responsible for translating complex chip architectures into manufacturable, high-performance layouts that meet the demanding power, performance, and area constraints of consumer wearable hardware. In this role, you will drive physical design strategy for Machine Learning IP across the full implementation flow for custom silicon targeting AR/VR platforms, working at the intersection of architecture, design, and process technology to shape the chips that define Meta's hardware roadmap.

Responsibilities

Lead physical design implementation across floorplanning, placement, clock tree synthesis, routing, and signoff for complex custom silicon blocks targeting AR/VR wearable platforms
• Collaborate with ML architects and designers to understand the ML workloads and develop custom physical design methodologies and recipes to optimize the PPA of ML compute datapath design blocks
• Define and drive physical design methodology, including timing closure strategies, power delivery network architecture, and design rule compliance for advanced process nodes
• Develop and own physical implementation flows, scripts, and automation to improve quality of results and reduce turnaround time across the design team
• Perform static timing analysis, power analysis, and physical verification including DRC, LVS, and ERC to achieve signoff closure
• Partner with package and board engineers to co-design bump maps, power delivery, and signal integrity solutions for wearable form-factor silicon
• Provide technical guidance to other engineers on physical design best practices and engage with foundry partners to resolve process-specific challenges

Minimum Qualifications
• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• 8+ years of experience in physical design implementation for complex digital SoCs or custom silicon, including floorplanning, placement, CTS, routing, and signoff
• Experience with advanced process nodes (3nm or below) including familiarity with foundry design rules, process design kits, and associated physical verification requirements
• Experience with industry-standard EDA tools for physical implementation and signoff, including static timing analysis, power analysis, and physical verification
• Experience defining or significantly contributing to physical design methodology, flows, or automation infrastructure across a multi-block or full-chip design
• Experience collaborating with RTL, architecture, and package engineering teams to co-optimize physical implementation decisions across the design hierarchy

Preferred Qualifications
• Experience developing physical design automation using scripting languages such as Python or Tcl to improve implementation efficiency and quality of results
• Experience with custom or semi-custom datapath design, including knowledge of standard cell characterization and library development
• Experience with physical design for power-constrained consumer wearable or mobile SoCs, including low-power design techniques such as multi-voltage domains and power gating
• Familiarity with 3D packaging technologies, chiplet integration, or advanced packaging co-design relevant to compact wearable form factors