Minimum qualifications:- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 10 years of experience in ASIC design verification methodology.
- 4 years of experience in leading/managing IP/Subsystem verification teams.
- Experience in UVM based IP and Subsystem/SoC verification.
Preferred qualifications:- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience in PSS (Portable Test and Stimulus Standard), formal or emulation based SimXL (Simulation Acceleration) methodologies.
- Familiarity with industry-standard EDA tools and methodologies.
- Track record to drive design verification methodology improvements in the team.
- Strong programming skills in Verilog, SystemVerilog, and Perl/Python.
Responsibilities - Lead and manage verification activities for complex subsystems and/or SoC.
- Develop all aspects of logic verification infrastructure and methodology for complex mobile SOC IP or subsystem blocks.
- Collaborate with design teams to ensure seamless integration of verification methodology into the design process.
- Optimize and improve verification methodologies to increase efficiency and effectiveness.
- Collaborate with both external and internal CAD teams to develop new verification solutions that can improve the quality and efficiency.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $192000 - $279000 (USD) 20% bonus target equity benefits
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