Job Details:

Job Description:

About the Role

We are seeking a Senior SoC Compute/Memory Subsystem Architect to define and drive the architecture of compute complexes and high-performance memory subsystems for next-generation IPU/DPU platforms.

This role is responsible for end-to-end architecture of CPU clusters, cache hierarchies, coherency models, and memory subsystems. You will optimize system-level performance, scalability, power efficiency, and programmability while ensuring seamless interaction with networking, storage, and accelerator subsystems in hyperscale environments.

What You'll Do

Key responsibilities will include but not limited to:

Compute Subsystem Architecture

1. Define architecture for IPU compute complexes (e.g., ARM/x86 clusters), including core selection, scaling strategy, and configuration tradeoffs

2. Architect compute subsystem roles (control plane, data plane assist, offload execution, management services)

3. Drive compute architecture decisions balancing performance, power, and area

Cache Hierarchy and Coherency Architecture

1. Define and evolve multi-level cache hierarchy (private/shared caches, system-level cache)

2. Architect coherency models across compute cores, accelerators, and IO subsystems (coherent vs non-coherent interactions)

3. Evaluate tradeoffs between latency, bandwidth, scalability, and coherence domain complexity

Memory Subsystem Architecture

1. Architect system memory subsystems including:

• DDR / LPDDR interfaces
• Memory controllers and scheduling policies
• Bandwidth provisioning and scaling strategies

2. Work with Performance architect in define memory access models for compute, network, and accelerator subsystems

3. Ensure optimal balance between latency-sensitive control workloads and bandwidth-intensive datapath workloads

IO Memory and Virtualization Architecture (SMMU/IOMMU)

1. Define architecture for SMMU/IOMMU supporting virtualization-heavy IPU workloads

2. Architect features such as:

• Multi-tenant isolation and security boundaries
• Shared vs isolated memory models

3. Ensure efficient interaction between host, IPU/DPU compute, and offload engines

System-Level Integration (Compute Network Storage)

1. Architect integration between:

• Compute subsystem
• Network subsystem (packet processing pipelines)
• Storage and accelerator subsystems

2. Optimize data movement across subsystems to minimize copies, latency, and bandwidth overhead.

3. Drive system architecture decisions for balanced SoC performance.

Power, Efficiency, and Scaling Strategy

1. Define compute and memory strategies for power efficiency and DVFS scalability.

2. Architect mechanisms for:

• Memory bandwidth throttling / prioritization
• Per-subsystem scaling

3. Optimize performance-per-watt at system level.

Multi-Generation Architecture Roadmap

1. Lead long-term roadmap for compute and memory evolution across IPU/DPU product generations

2. Define scaling strategies for:

• Core count and frequency
• Memory bandwidth and capacity
• Cache scaling and topology

3. Ensure backward compatibility and smooth migration across product lines

Cross-Functional Leadership

1. Collaborate with teams across:

• Networking subsystem (NSS)
• SoC fabric/interconnect
• Firmware, OS, and drivers
• Validation and performance modeling and testing

2. Drive architecture alignment and resolve cross-domain tradeoff

Behavioral traits that we are looking for: (soft skills that you would like to see in a candidate)

• Strategic thinker: Ability to define long-term architecture vision and align stakeholders
• Technical leadership: Influences across teams without direct authority
• Problem solver: Approaches complex system challenges with structured thinking
• Collaboration: Builds strong partnerships across engineering disciplines
• Customer-focused mindset: Translates real-world workload needs into solutions
• Adaptability: Navigates ambiguity and evolving technical requirements
• Ownership mindset: Drives initiatives from concept through execution

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Note:

For information on Intel's immigration sponsorship guidelines, please see

Intel U.S. Immigration Sponsorship Information

Minimum Qualifications and Experience:

Batchelor's degree in Electrical Engineering, Computer Engineering, or in a STEM related Field of Study.

You must have 7 + years of experience in the following:

• SoC / CPU / memory subsystem architecture
  CPU architecture and cache hierarchies
• Memory subsystems (DDR/HBM, controllers, QoS)
  Coherent/Non-Coherent interconnect architectures
• Experience in system-level performance and PPA tradeoff analysis
• Drive architecture definition from concept to silicon

Preferred Qualifications and Experience:

• Post Graduate degree in Electrical Engineering, Computer Engineering, or in a STEM related Field of Study
• ARM and x86 compute and memory subsystem experience, including NUMA systems, cache coherency, or large scale platform architectures.
• Experience with IPU / SmartNIC or accelerator centric SoCs, particularly in cloud and hyperscale environments
• Familiarity with PCIe, CXL, and memory semantics for high performance IO.
• Track record of multi generation architectural ownership and mentoring other architects.

Join us in building a brighter future through technology innovation!

Job Type:
Experienced Hire

Shift:
Shift 1 (United States of America)

Primary Location:
US, California, Santa Clara

Additional Locations:
US, Arizona, Phoenix, US, California, Folsom, US, California, San Jose, US, Colorado, Fort Collins, US, Texas, Austin

Business group:
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Position of Trust
N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $164,470.00-269,100.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.The application window for this job posting is expected to end by 07/31/2026