OverviewAs a
Senior Quantum Foundry Technologist & Library Specialist in the Quantum 1st Party Hardware System-on-a-Chip (SOC) team, you will play a critical leadership role in advancing the development of Microsoft's quantum Application-Specific Integrated Circuit (ASIC) Foundry and Library Interface. Your responsibilities will include interfacing and establishing relationships with internal/external foundries, and creation of library Process-Development-Kits (PDK) for Cryo/Quantum System-on-a-Chip (SOC) implementation.
Throughout the program lifecycle, you will engage with cross-functional teams-including architecture, quantum, verification, analog, physical design and vendors - to ensure that the design meets specifications and is successfully implemented and verified. This role requires proficiency and technical expertise, excellent communication skills, and the ability to manage complex design challenges in a collaborative environment.
This is a unique opportunity to be at the forefront of quantum hardware innovation. You will collaborate with leading physicists, quantum theorists, quantum experimentalists, research engineers, systems engineers, technical program managers, supply chain experts, cloud architects, and external partners to accelerate the scale-up of topological qubits and quantum systems that unlock unprecedented scientific and business value. If you are energized by complex program management challenges, thrive in ambiguity, and have a passion for foundational technologies that redefine what's possible, we invite you to join us and help shape the future of quantum computing.
Responsibilities- Audit external foundries to find a suitable partner for long-term engagement for Microsoft quantum/cryo silicon programs. Evaluate their solutions for materials/process tailoring to match our needs. Create long-term evolution plans with vendors for evolving process needs for future quantum products.
- Lead technical interactions with external foundries both in pre-silicon design and post silicon development as well as continuous improvement for Yield and performance during production manufacturing stage to ensure Best-in-class Microsoft first-party silicon.
- Find / define design development libraries and re-characterizations for standard cells and analog design PDKs at cryo temperatures.
- Define and design engineering structure in testchip for technology interception and enablement including data collection, analysis and model-silicon characterization.
- Compile and analyze data using common statistical techniques and effectively present key results along with recommended actions; practice continuous improvement and yield optimization and analyze products to ensure manufacturability and data sheet compliance
- Other
- Embody our culture and values.
QualificationsRequired/minimum qualifications- Doctorate in Physics, Engineering, or related field AND 1+ year(s) experience in industry or in a research and development environment, could include completion of a post doctoral research position
- OR Master's Degree in Physics, Engineering, or related field AND 4+ years experience in industry or in a research and development environment
- OR Bachelor's Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment
- OR equivalent experience
Other Requirements:- Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings:
- Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
- Citizenship & Citizenship Verification: This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations (ITAR) or Export Administration Regulations (EAR), the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their U.S. permanent residency or other protected status (e.g., under 8 U.S.C. a7 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.
Preferred qualifications - Doctorate in Physics, Engineering, or related field AND 3+ years experience in industry or in a research and development environment, could include completion of a post doctoral research position
- OR Master's Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment
- OR Bachelor's Degree in Physics, Engineering, or related field AND 8+ years experience in industry or in a research and development environment
- OR equivalent experience
- 5+ years of experience in device physics, foundry design collateral, process qualification, broad fabrication process experience, device reliability, statistical analysis, yield improvement, and physical failure analysis techniques.
- 5+ years of experience in Testchip design experience including test structure definition, schematics and layout design,
Simulation Program with Integrated Circuit Emphasis (SPICE), functional verification and test implementation. - Awareness of PDKs/Libraries for design development and knowledge of how to scale this for cryo temperatures.
- Effective communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.
- Experience with device-level measurements and associated test equipment, data analysis, modeling, simulation, targeting and projection.
- Probability and statistics background, including Design of Experiments (DOE's)
- Experience in Leading cross-functional teams and understands program/project management.
- Proficient in product yield/performance analysis, and design technology co-optimization.
- Model based problem-solving skills through data analysis and understanding of SOC design features, fabrication (FAB) process interactions and test methodology.
- Electronic Design Automation (EDA) tools from Cadence, Synopsys, Siemens for device and Intellectual Property (IP) study.
- Proficient in data analysis tools like excel, JMP, etc.
- Custom process and custom library development.
- Product and test engineering, and Automated Test Equipment (ATE) test program methodologies.
- SPICE model development.
- Analog design with automation and script; proficient with latest mixed-signal design flows and tools.
- Digital design knowledge in floor planning, Static Timing Analysis (STA); taking Register Transfer Level (RTL) to Graphic Data System (GDS) and optimize for Power Performance Area (PPA)
- Knowledgeable in:
- Coding using various languages including but not limited to Python, Java and C++
- Leveraging and designing/optimizing Artificial Intelligence/Machine Learning (AI/ML)
- Design for Testability (DFT) and Design for Manufacturability (DFM) techniques 9+ years of related technical engineering experience with a BSEE equivalent or higher in Electrical Engineering, Material Science or related field.
- 8 + years of experience in semiconductor process development and manufacturing.
- 5+ years of experience in and technology evaluation, testchip and modeling.
- Ability to leverage AI tools to drive innovation and efficiency (e.g., performance modeling and analysis, research gathering, day to day task automation).
- Ability to work in an 2AI-first2 environment using modern AI tools to accelerate discovery through hardware development.
#Quantum #QuantumCareers #MDQCareers
Quantum Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800.00 - $234,700.00 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200.00 - $261,000.00 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
https://careers.microsoft.com/us/en/us-corporate-pay
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.
