The Role:We are looking for a Senior QPU Design Engineer to join our Processor Design team at Oxford Ionics, now part of IonQ. You will be responsible for integrating all the features required to operate our quantum computers into complex chips, contributing to the team's mission of advancing the design of high performance quantum processing units. You will work closely with scientists and fabrication engineers to bring new designs for ion trapping chips into production, and you will play an important part in shaping the hardware behind our work building the world's most advanced quantum systems.
Responsibilities:
In this position you will turn operational requirements into chip layout, supporting the delivery of devices that enable new technologies. You will have the opportunity to expand the range of features our chips support, contributing directly to the goal of building utility scale quantum computers.
- Guiding chips through the design process, from requirements to layout and tape out
- Laying out complex multi layer chips, including metal track routing and interfaces with photonics and CMOS
- Collaborating with scientists to discuss their requirements and settle on specifications
- Coordinating with other teams to ensure feasibility and compatibility
- Taking charge of projects independently and owning delivery of the final tape out
Requirements:You will need experience translating design requirements into features, alongside hands on experience in chip layout. We are looking for someone who can work across teams to discuss the many aspects of chip design, understand how different parts of a chip influence and constrain one another, take on layout work themselves, and contribute effectively within a fast moving and highly technical team. You will need to drive the design process, solve problems as they arise, and take responsibility for delivery.
We're looking for someone who can guide chips through the full design process, from requirements through to layout and tape-out. You will have experience laying out complex, multi-layer chips, including metal-track routing and interfaces with photonics and CMOS. You'll collaborate with scientists to understand their requirements and agree specifications, while coordinating with other teams to ensure feasibility and compatibility. You'll also be comfortable taking charge of projects independently and owning the delivery of the final tape-out.
You'd be a great fit with:- Experience in scripted generation of layout, using GDSFactory in Python or similar
- Experience using Cadence for IC layout
- Experience in ion trap design, photonics design or IC packaging
US Salary Banding:$124,000 - $186,000
If this role has a commission structure, the compensation range below just reflects the base compensation range.
Wage Transparency:
£75,200-£112,800 GBP
Compensation will vary based on individual factors such as education, qualifications, and experience of the final candidate(s), specific office location, and calibration against relevant market data and internal team equity. Posted base salary figures are subject to change as new market data becomes available. Our benefits include comprehensive medical, dental, and vision plans, matching 401(k), unlimited PTO and paid holidays, parental/adoption leave, legal insurance, and a home technology stipend. Details of participation in these benefit plans will be provided when a candidate receives an offer of employment.
