Astera Labs

Senior Principal System Validation Engineer

Astera Labs • $205K — $255K *
San Jose, CA 95123In-Person
Telecommunications & Hardware
11 - 15 years of experience
1 month ago
Job Overview by Ladders

Qualifications

  • Bachelor's degree in Electrical or Computer Engineering, with a Master's preferred.
  • 12+ years of experience with complex SoC/silicon products in Server, Storage, or Networking applications.
  • Basic understanding of x86/ARM architecture and UEFI/Linux boot sequence.
  • Ability to prioritize multiple tasks and work independently with minimal supervision.
  • Entrepreneurial mindset with a customer-centric approach.

Responsibilities

  • Develop and conduct system validation tests utilizing advanced Data Center equipment.
  • Understand and meet performance/functionality requirements for Data Center systems using Astera Labs' products.
  • Create and execute a comprehensive validation plan and automate IC testing.
  • Design experiments to diagnose unexpected system behavior effectively.
  • Collaborate directly with key customers to identify their specific needs and demonstrate product capabilities.

Benefits

  • Opportunity to work with cutting-edge Data Center technology.
  • Direct collaboration with key customers in innovative Artificial Intelligence and Machine Learning applications.
  • Emphasis on a strong entrepreneurial culture and customer-centric approach.
  • Engagement in high-impact validation processes that influence product quality and performance.
Full Job Description
Job Description
  • Develop and perform system validation tests using leading-edge Data Center equipment and scalable automation platforms. The validation team holds customers' system requirements in the highest regard and is solely responsible for certifying a product's conformance to this high bar.
  • Understand the performance and functionality requirements our ICs must deliver to enable customers developing Data Center systems using Astera Labs' game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications.
  • Formulate a comprehensive validation plan, automate the testing of ICs and board products in a data-centric manner, design experiments to root-cause unexpected behavior, report results and specification compliance in an automated fashion.
  • Work with key customers directly to understand their care-abouts and highlight the unique capabilities and performance of Astera Labs' solutions.

Basic qualifications
  • Strong academic and technical background in Electrical or Computer Engineering. At a minimum, a Bachelor's is required, and a Master's is preferred.
  • ≥12 years' experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
  • Basic understanding of x86/ARM architecture, UEFI/Linux boot sequence.
  • Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer/internal meetings in advance, and to work with minimal guidance and supervision.
  • Entrepreneurial, open-mind behavior and can-do attitude. Think and act with the customer in mind!

Required experience
  • Hands-on, thorough knowledge of high-speed protocols like CXL, PCIe, NVMe, or Ethernet.
  • Experience with Silicon/System bring-up, validation, and debug experience, including in customer systems.
  • A strong background in developing bench automation techniques, especially using Python, with emphasis on execution efficiency, repeatability, data analysis and reporting.
  • Experience with lab equipment including protocol analyzers, in-circuit debuggers, and CPU-based tool suites.

Preferred experience
  • Working knowledge of C or C++ for embedded FW and device drivers.
  • Working knowledge of SerDes architecture including Tx/Rx equalization, adaptation, CDR, block level requirements and SerDes link jitter budget. Experience with PAM4 SerDes is a huge bonus!
  • Familiarity with PCIe compliance standards and ability to follow and be involved in compliance consortiums to adapt the tests to be run from X86/ARM based platforms.
  • Knowledge of schematic capture and PCB layout tools from Cadence Allegro, Altium, etc.
  • Knowledge of simulation tools such as Keysight ADS, Mathworks QCD, etc. for IBIS-AMI analysis.

The base salary range is $205,000.00 USD - $255,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

About Astera Labs

Astera Labs is a semiconductor company that designs and develops purpose-built connectivity solutions for data-centric systems. The company's portfolio of products includes system-aware semiconductor integrated circuits (ICs), boards, and intellectual property (IP) that are used in data center servers, storage, and networking equipment. Astera Labs' products are designed to improve the performance, latency, and power consumption of data-centric systems. The company was founded in 2018 and is headquartered in Santa Clara, California.
Learn more about Astera Labs
Size
51 employees
Industry
Manufacturing & Automotive
Net Income
-$3 million
Founded
2018
Revenue
$5 million
NASDAQ
ALAB
* Ladders Estimates

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