Marvell Technology

Senior Principal Engineer, Physical Design

Marvell Technology$179K — $266K *
Consumer Technology
11 - 15 years of experience
Job Overview by Ladders

Qualifications

  • Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or related field.
  • 15+ years of progressive experience in back-end physical design and verification with leadership roles.
  • Proven track record in managing complex SoC projects and delivering high-quality tapeouts under tight schedules.
  • Deep expertise in hierarchical physical design strategies and methodologies for advanced process nodes.
  • Strong understanding of ASIC design flow, RTL integration, and timing closure.

Responsibilities

  • Shape the long-term vision for physical design capabilities and infrastructure.
  • Lead RTL-to-GDSII implementation for multiple SoC programs.
  • Mentor and develop engineering talent, fostering innovation and collaboration.
  • Oversee team structure, hiring, and performance management to build a high-performing organization.
  • Drive cross-functional collaboration and resolve conflicts effectively.
  • Manage project schedules, resources, and risks to align with business goals.
  • Collaborate with EDA vendors on tool evaluation and deployment.

Benefits

  • Employee stock purchase plan with a 2-year look back.
  • Family support programs for work-life balance.
  • Robust mental health resources for emotional well-being.
  • Recognition and service awards to celebrate employee contributions and milestones.
Full Job Description

Your Team, Your Impact

Built on decades of expertise and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you’ll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, and networking applications.

What You Can Expect

As a senior leader in the central physical design team, you will:

Shape the long-term vision for physical design capabilities and infrastructure in alignment with company-wide technology strategy.

  • Lead RTL-to-GDSII implementationfor multiple SoC programs, overseeing synthesis, floorplanning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, and physical verification (DRC/LVS).
  • Providestrategic leadership and technical directionto physical design teams, ensuring successful and timely tapeouts of complex, high-performance SoCs.
  • Mentor and develop engineering talent, fostering a culture of innovation, collaboration, and continuous improvement.
  • Oversee team structure, hiring, performance management, and career development to build and retain a high-performing physical design organization.
  • Drive cross-functional collaboration with design teams to influence design decisions and ensure successful project execution.
  • Navigate and resolve cross-functional conflicts effectively, fostering alignment and maintaining momentum across diverse teams.
  • Drive thedevelopment and adoption of next-generation physical design methodologies, flows, and automation to improve productivity and design quality.
  • Manage project schedules, resources, and risk, ensuring alignment with business goals and customer requirements.
  • Represent the physical design function in cross-org and executive-level discussions, contributing to long-term technology and product strategy.
  • Collaborate with EDA vendors and internal CAD teams to evaluate and deploy new tools and technologies.

What Were Looking For

  • Bachelors, Masters, or PhD degree in Electrical Engineering, Computer Engineering, or a related field.
  • 15+ years of progressive experience in back-end physical design and verification, including significant leadership roles.
  • Proven track record of leading and scaling physical design teams, managing complex SoC projects, and delivering high-quality tapeouts under aggressive schedules.
  • Deep expertise in hierarchical physical design strategies, methodologies, and advanced process node challenges.
  • In-depth understanding of current design technologies used in major foundries.
  • Strong understanding of ASIC design flow, RTL integration, synthesis, and timing closure.
  • In-depth knowledge of modern EDA tools and flows.
  • Proficient in automation and scripting using Makefile, Tcl, Python, or Perl to enhance design efficiency and flow robustness.
  • Strong communication and collaboration skills, with the ability to influence cross-functional teams and executive stakeholders.
  • Experience in developing and deploying advanced physical design methodologies and flows.
  • Familiarity with AI/ML-driven optimization in physical design tools is a plus.

Expected Base Pay Range (USD)

179,900 - 266,180, $ per annum

The successful candidates starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

This role is eligible to participate in Marvells bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the companys long-term success.

Additional Compensation and Benefit Elements

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through lifes most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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About Marvell Technology

Marvell Technology is a semiconductor company that designs and develops analog, mixed-signal, and digital signal processing integrated circuits. The company's product portfolio includes processors, connectivity, storage, and security solutions. Marvell's customers operate in various industries, including data center, enterprise, automotive, industrial, and consumer electronics. The company was founded in 1995 and is headquartered in Santa Clara, California.
Learn more about Marvell Technology
Size
6,729 employees
Market Cap
$30.6 billion
Industry
Net Income
-$277.3 million
Founded
2013
5 Year Trend
+14.2%
Revenue
$2.9 billion
NASDAQ

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