This role is a senior technical authority responsible for defining, aligning, and governing Physical Design Architecture, Technology aspects, Foundry selection & PPA. The technologist serves as the primary interface between the internal SoC Physical Design organization and the foundry, systems team & ensure competitive edge. Foundry (TSMC) Interface & Ownership • Primary technical point of contact with TSMC for Physical Design. • Technical discussions with foundry team internal and external with regards to foundry selection • Work with foundry & technology to define requirements for signoff & collaterals. AI Initiative • Lead an AI initiative focusing cost reduction of MCU development • Drive the AI strategy of Physical team in conjunction with methodology teams and external vendors. • Pilot AI initiatives within organization including scoping, definition & implementation. Physical Design Architecture Definition and Feasibility • Work with system architects, Architecture team & Chip leads to ensure physically realizable architecture for MCU designs • Drive Physical Partitioning, latency, pipeline planning, IO & AC requirement with leads. • Align Die-size & PPA targets & KPI for SoC/MCUs Qualifications • Master's degree in electrical, Electronics, or Computer Engineering. • 18-20+ years of experience in Physical Design with multiple -node tapeouts. • Experience handling MCU designs, Familiarity with Architecture & Design We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process. Are you ready to join our team and shape the future with us? Videos To Watch https://www.youtube.com/embed/k-zs4tB6nNc