Cornelis Networks

Senior Manager, ASIC Design Engineering

Cornelis Networks$150K — $180K *
Telecommunications & Hardware
11 - 15 years of experience
Job Overview by Ladders

Qualifications

  • 15+ years in semiconductor industry focused on high-performance designs, with at least 5 years in management.
  • B.S. or M.S. in Computer/Electrical Engineering or related field.
  • Deep understanding of Design, Verification, Emulation, and Physical Design interactions.
  • Proven track record of leading large teams through full-cycle ASIC product launches remotely.
  • Strong expertise in microarchitecture development, RTL coding (Verilog/System Verilog), and timing closure.
  • Familiarity with industry standards such as PCIe, Ethernet, UCIe, and UALink.
  • Ability to optimize for PPA (power, performance, area) and integrate subsystems.

Responsibilities

  • Own ASIC RTL delivery schedules, tracking and reporting progress against plans.
  • Utilize data-driven insights to forecast schedule risks and adjust resource allocations.
  • Align RTL schedules with DV and emulation enablement, managing feedback loops efficiently.
  • Facilitate handoffs between design teams and physical design to ensure high-quality RTL submission.
  • Lead headcount planning, identifying skill gaps and executing talent acquisition strategies.

Benefits

  • Comprehensive health coverage including medical, dental, and vision insurance.
  • Disability and life insurance, plus pet insurance available.
  • Generous paid holidays and Open Time Off for work-life balance.
  • 401(k) plan with company match to support retirement savings.
  • Flexible spending account options for dependent care expenses.
Full Job Description
Cornelis Networks is looking for a Senior ASIC Design Engineering Manager to lead and grow our RTL design engineering team. Reporting to the VP of ASIC Engineering, with direct exposure to executive leadership, this leader will manage a team of talented design engineers and drive full-lifecycle development of Cornelis' next-generation, high-performance networking ASICs. The role is accountable for building and driving RTL implementation schedules across all SoC subsystems and full-chip milestones. Success requires deep hands-on expertise in advanced RTL design implementation, methodologies, and SoC flows, from microarchitecture definition through RTL delivery, tape-out readiness, and cross-functional execution with Architecture, Design Verification, Emulation, and Physical Design. This leader will also own headcount planning, hiring, and organizational strategy to build a nimble, efficient, world-class design team. Exposure to AI-based design flows and methodology is preferred.

This role is intended for a senior engineering leader who can combine hands-on ASIC RTL design expertise with disciplined program execution, cross-functional coordination, and team building at scale.

Key Responsibilities
  • Own ASIC RTL delivery schedules across major milestones by tracking, monitoring, and reporting progress against committed plans.
  • Utilize data-driven insights to predict schedule risks and proactively reallocate human resources to keep the project on track.
  • Align RTL delivery schedules with DV and emulation enablement and manage feedback loops and dependencies efficiently.
  • Facilitate physical design handoffs by ensuring design teams provide high-quality RTL and constraints that minimize timing-closure iterations. Track physical design feedback and delivery schedules to support physical design signoff and tape-out milestones.
  • Lead long-term headcount planning and organizational design for the ASIC department. Identify skill gaps and execute global talent acquisition strategies that support the product roadmap.

Minimum Qualifications
  • 15+ years in the semiconductor industry, preferably in high performance designs on advanced technology nodes, with at least 5 years in people management
  • B.S. or M.S. in Computer Engineering, Electrical Engineering, or related technical field, or equivalent practical experience
  • Deep understanding of the interaction between Design, Verification, Emulation, and Physical Design teams. You must know "how the work gets done" to manage the people doing it.
  • Proven ability to lead large engineering organizations through multiple full-cycle ASIC product launches in a remote environment. Ability to coordinate across multiple projects, manage risks and escalations, and work under tight schedules and budget constraints.
  • Strong technical expertise in microarchitecture development, RTL coding (Verilog/System Verilog), synthesis, STA/timing closure, physical design, and verification methodologies.
  • Exposure to one or more industry standards/protocol stacks such as PCIe, Ethernet, UCIe, UALink.
  • Demonstrated ability to optimize designs for PPA (power, performance, area) and to integrate major subsystems (interconnect, I/O, memory).


Preferred Qualifications
  • Exposure to AI based design implementation and verification flows, scripting for automation, milestone tracking and flow integration
  • Experience building globally distributed ASIC design teams and scaling engineering practices in a remote environment.


Location: This is a remote position for employees residing within the United States.

We offer a competitive compensation package that includes equity, cash, and incentives, along with health and retirement benefits. Our dynamic, flexible work environment provides the opportunity to collaborate with some of the most influential names in the semiconductor industry.

At Cornelis Networks your base salary is only one component of your comprehensive total rewards package. Your base pay will be determined by factors such as your skills, qualifications, experience, and location relative to the hiring range for the position. Depending on your role, you may also be eligible for performance-based incentives, including an annual bonus or sales incentives.

In addition to your base pay, you'll have access to a broad range of benefits, including medical, dental, and vision coverage, as well as disability and life insurance, a dependent care flexible spending account, accidental injury insurance, and pet insurance. We also offer generous paid holidays, 401(k) with company match, and Open Time Off (OTO) for regular full-time exempt employees. Other paid time off benefits include sick time, bonding leave, and pregnancy disability leave.

About Cornelis Networks

Cornelis Networks is a technology company that provides software solutions for the financial industry. The company's products include a trading platform for cryptocurrencies and a risk management system for banks and other financial institutions. Cornelis Networks was founded in 2018 and is headquartered in Amsterdam, Netherlands.
Learn more about Cornelis Networks
Size
10 employees
Industry
Founded
2018

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