Join Astera Labs as a
Senior Digital Design Engineer to drive the design and implementation of next-generation digital designs for high-performance AI connectivity solutions. In this role, you'll focus on CPU subsystem development and security architecture, working on complex blocks from micro-architecture through silicon bring-up.
You'll collaborate closely with verification, physical design, and DFT teams to deliver industry-leading products that power the world's most advanced data centers. This is an opportunity to shape the security and compute foundations of connectivity solutions enabling rack-scale AI infrastructure at hyperscale.
Key Responsibilities- RTL Design & Implementation
- Own the RTL implementation of complex digital designs from micro-architecture through sign-off
- Design and implement CPU subsystems and embedded processor interfaces
- Develop security-focused digital blocks including secure boot, cryptographic engines, and trusted execution environments
- Verification & Quality
- Collaborate with verification teams to review test plans and debug issues
- Support efforts to achieve timing closure and implement Design-for-Test (DFT) features
- Accountable for quality and overall design success with the support of senior engineers
- Methodology & Automation
- Scripting and automation for ASIC methodology improvement
- Contribute to design infrastructure that improves team productivity and design quality
Basic Qualifications- Bachelor's degree in Electrical Engineering or equivalent
- 3+ years of experience developing SoC/silicon products in Server, Storage, and/or Networking markets
- Expertise in RTL coding with SystemVerilog and synthesis with Synopsys or Cadence
- Experience with CPU subsystem design or embedded processor integration (RISC-V, ARM, or similar architectures)
- Understanding of security fundamentals in silicon design (secure boot, root of trust, cryptographic implementations)
- Experience with clocking, CDC, and RDC methodologies
- Proficiency in SystemVerilog and Python in a production environment
Preferred Qualifications- Experience designing or integrating security IP (cryptographic accelerators, secure enclaves, key management)
- Familiarity with high-speed protocols-PCIe Gen 6/7, Ethernet, UALink, or UCI
- Experience with CMOS nodes (≤7nm)
- Exposure to embedded firmware development or secure firmware boot flows
- Experience with functional and formal verification at block and chip level
- Familiarity with UVM-based verification methodologies
Base salary range is $135,000 to $195,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.
