We are looking for a Senior Design Verification engineer to verify ASIC/SoC designs using SystemVerilog/UVM, develop automated test environments, and drive bug closure throughout the development cycle for one of our clients in Sunnyvale, CA. Responsibilities • Key Responsibilities: 1. Verification Planning: Develop and implement verification plans that outline the testing strategy for new designs. 2. Test Development: Create and execute test cases, simulations, and scripts to validate designs against specifications. 3. Collaboration: Work closely with design engineers, software developers, and other stakeholders to understand design requirements and ensure comprehensive verification coverage. 4. Debugging: Identify, analyze, and resolve design issues and bugs through systematic testing and debugging techniques. 5. Documentation: Maintain detailed documentation of verification processes, test results, and design changes. 6. Continuous Improvement: Contribute to the development of best practices and methodologies for design verification. Requirements Required Skills: • Technical Proficiency: Strong knowledge of hardware description languages (HDLs) like Verilog or VHDL, and familiarity with simulation tools. • Analytical Skills: Ability to analyze complex systems and troubleshoot issues effectively. • Programming Skills: Proficiency in programming languages such as Python, C/C++, or SystemVerilog for automation and test development. • Communication: Excellent verbal and written communication skills to collaborate with cross-functional teams. Minimum Qualifications B.S or M.S degree in Electrical Engineering, Computer Engineering or Computer Science Hands-on experience in Verilog, SystemVerilog, C/C++ based verification, and UVM methodology Experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies Experience in EDA tools and scripting (Python, Perl, Shell) used to build tools and flows for verification environments. Experience in architecting and implementing Design Verification infrastructure and executing the complete verification cycle Preferred Qualifications Experience in the development of UVM based verification environments from scratch Experience with Design verification of Data-center applications like Video, AI/ML, and Networking designs Experience with revision control systems like Mercurial(Hg), Git or SVN Experience with verification of ARM/RISC-V based sub-systems or SoCs