OverviewRambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Senior/Lead Design Verification Engineer to join our Memory Controller IP team in Hillsboro, Oregon. The successful candidate will participate in pre-silicon RTL Verification activities related to Memory Controller SoftIP development, on leading-edge DDR, HBM, and GDDR DRAM controller technologies. This is a Full Time position, reporting to the local onsite manager of the Memory Controller IP Verification team .
Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite while also allowing for two days of remote work.
Responsibilities
- Testbench and test sequence development for verification of new controller technologies and features
- Functional coverage planning, coverage item coding, and test suite augmentation to achieve Functional Coverage
- Regression test development, monitoring, debug/triage, and correction to test environment, sequences, debug of controller RTL design
- Development & support of Verification environment scripting and capabilities
Qualifications
- Bachelors Degree or above in EE/CS, minimum 7 years experience with HDL logic Design-Verification
- System Verilog testbench, Verilog/System Verilog logic design/RTL fluency a must
- Pre-existing Experience / familiarity with DDR DRAM technology a strong preference
- Working experience with Python and TCL scripting languages preferred
Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program, and gym membership.
The US salary range for this full-time position is $108,300 to $201,100. Our salary ranges are determined by role, level and location. The successful candidate’s starting pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.
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