Microsoft

Senior Custom Memory Layout Design Engineer

Microsoft$119K — $234K *
Telecommunications & Hardware
Less than 5 years of experience
Job Overview by Ladders

Qualifications

  • Doctorate or Master's in Electrical/Computer Engineering or related field with relevant experience OR Bachelor's degree with extensive technical experience.
  • 5+ years of custom memory layout experience preferred, with a focus on SRAMs, Register Files, caches, or related architectures.
  • Familiarity with Cadence Virtuoso and Siemens/Mentor Calibre for physical verification tasks.
  • Knowledge of advanced-node design verification, including DRC, LVS, and ERC principles.
  • Expertise in FinFET or Gate-All-Around technologies and understanding of memory integration processes.
  • Strong automation skills using scripting languages like Python, SKILL, or TCL.

Responsibilities

  • Drive physical implementation of custom memory layouts and integrate advanced technologies.
  • Collaborate with various engineering teams to optimize memory IP for power, performance, and manufacturability.
  • Ensure compliance through physical verification processes including DRC and LVS.
  • Deliver comprehensive production-ready memory IP collateral for SoC integration.
  • Enhance methodologies and automation flows for custom memory layouts.
  • Work with engineers and layout teams to resolve technical issues and meet deadlines.
  • Identify risks and communicate technical status in multi-program environments.

Benefits

  • Access to comprehensive benefits package including health insurance and retirement planning.
  • Opportunities for professional development and training.
  • Collaborative work environment supporting innovation and creativity.
  • Flexible work arrangements to support work-life balance.
Full Job Description
Responsibilities
  • Drive physical implementation of custom SRAM, Register File (RF), cache, and memory layouts in advanced process technologies, including floorplanning, hierarchy development, placement, routing, and physical integration.
  • Collaborate with circuit design, architecture, physical design, CAD, foundry, and SoC teams to optimize memory IP for power, performance, area (PPA), reliability, manufacturability, and integration readiness.
  • Perform physical verification and signoff activities including DRC, LVS, ERC, antenna, density, EMIR, reliability analysis, debug, and closure support.
  • Deliver production-ready memory IP collateral, including GDS/OASIS, LEF abstracts, integration views, documentation, and signoff packages for SoC integration.
  • Develop and improve custom memory layout methodologies, design-rule adoption, automation flows, and productivity solutions using SKILL, TCL, or similar scripting languages.
  • Partner with internal engineers, contractors, and external layout teams to review deliverables, resolve technical issues, and support execution to program milestones.
  • Identify technical risks, communicate status and tradeoffs clearly, and support multiple custom memory programs across advanced technology nodes with high-quality execution.


Qualifications

Required Qualifications
  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.

Other Requirements:

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

Preferred Qualifications
  • 5+ years of custom memory layout experience including SRAMs, Register Files, cache structures, embedded memories, or high-density memory architectures.
  • Experience using Cadence Virtuoso and Siemens/Mentor Calibre physical verification tools.
  • Experience with DRC, LVS, ERC, antenna, and physical signoff verification on advanced-node designs.
  • Experience with FinFET and/or Gate-All-Around process technologies.
  • Experience collaborating with circuit design teams to optimize memory IP for power, performance, and area.
  • Experience owning or contributing to custom memory IP deliveries from specification through tapeout, including SRAM, Register File (RF), cache, or related embedded memory architectures.
  • Strong understanding of SRAM and RF architecture fundamentals, including bitcell integration, row/column peripheral circuitry, assist circuitry, redundancy implementation, and layout tradeoffs.
  • Experience supporting memory integration through LEF/abstract generation, timing or physical collateral development, signoff documentation, and SoC integration readiness.
  • Experience with EMIR analysis and reliability signoff using Ansys Totem, Cadence Voltus, or equivalent tools.
  • Strong automation and scripting skills using Python, SKILL, TCL, Perl, or similar languages to improve layout productivity and quality.
  • Experience with advanced technology nodes such as 5nm, 3nm, or beyond, and familiarity with analog/mixed-signal layout considerations.
  • Experience working with geographically distributed teams, contractors, vendors, or design-service partners to deliver layout milestones.


Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
https://careers.microsoft.com/us/en/us-corporate-pay

This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.

About Microsoft

Microsoft is an American multinational corporation that develops, manufactures, licenses, supports, and sells a range of software products and services. Microsoft’s devices and consumer (D&C) licensing segment licenses the Windows operating system and related software, Microsoft Office for consumers, and the Windows Phone operating system. The company’s computing and gaming hardware segment provides Xbox gaming and entertainment consoles and accessories, second-party and third-party video games, and Xbox Live subscriptions; surface devices and accessories; and Microsoft PC accessories. Its phone hardware segment offers Lumia smartphones and other non-Lumia phones. Its D&C segment provides Windows Store, Xbox Live transactions, and Windows phone store; search advertising; display advertising; Office 365 Home and Office 365 Personal; first-party video games; and other consumer products and services as well as operating retail stores. Microsoft’s commercial licensing segments license server products, including Windows Server, Microsoft SQL Server, Visual Studio, System Center, and related Client Access Licenses (CALs); Windows Embedded; Windows operating system; Microsoft Office for business, including Office, Exchange, SharePoint, Lync, and related CALs; Microsoft Dynamics business solutions; and Skype. Its commercial segment offers enterprise services, including premier support services and Microsoft consulting services; commercial cloud comprising Office 365 Commercial, other Microsoft Office online offerings, Dynamics CRM Online, and Microsoft Azure; and other commercial products and online services. The company markets and distributes its products through original equipment manufacturers, distributors, and resellers, as well as online.

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Learn more about Microsoft
Size
181,000 employees
Market Cap
$1,762.4 billion
Industry
Net Income
$51.3 billion
Founded
1975
5 Year Trend
+15.5%
Revenue
$153.2 billion
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