Minimum qualifications:- Bachelor's degree in Electrical Engineering, Computer Engineering, a related field, or equivalent practical experience.
- 10 years of experience in Test Engineering and Post-Silicon Validation, with 5 years of experience in CMOS.
- 2 years of experience in a technical leadership or lead architect role.
- Experience with Analog Mixed-Signal Silicon.
- Experience programming for lab automation and data analysis.
Preferred qualifications:- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with benchtop measurement equipment (High-bandwidth Oscilloscopes, Spectrum Analyzers, BERTs, VNAs).
- Vendor management experience working with OSATs and PCB fabrication houses.
- Familiarity with high-speed serial protocols (MIPI).
- Proven track record developing C /Python test code for automated test equipment.
About the jobAs a Senior Test and Post-Silicon Validation Lead, you will drive the bring-up, characterization, and high-volume manufacturing (HVM) release of our next-generation Analog Mixed-Signal (AMS) ASICs. In this critical leadership role, you will bridge the gap between design, DFT, and product engineering, ensuring zero-defect quality and optimized cost-of-test for our upcoming product lines. You will architect ATE test strategies and guide a small team of engineers through complex yield and performance bottlenecks.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $240000 - $333000 (USD) 25% bonus target equity benefits
Learn more about benefits at Google .
Responsibilities- Lead and mentor a team of test and validation engineers through the entire post-silicon lifecycle, from first-silicon bench bring-up to ATE production release. Partner with IC Design and DFT teams during the pre-tapeout phase to define Post SIlicon Test Process and Design requirements.
- Design, develop, and debug multi-site ATE test programs (Advantest V93000 or Teradyne UltraFLEX) focusing on high-efficiency parallel testing for digital and AMS blocks.
- Drive exhaustive post-silicon validation across PVT corners. Ensure strict bench-to-ATE correlation for critical high-speed interfaces and analog blocks.
- Oversee the architecture and schematic review of complex loadboards and probe cards, ensuring Signal Integrity and Power Integrity (SI/PI) standards are met for high-frequency measurements.
- Automate data collection from wafer test.
