Overview:
Job Title: Senior ASIC / SoC Network-on-Chip Design Engineer or Senior ASIC Design Engineer
Location: Mountain View CA (onsite - Hybrid)
Job Type: FullTime.
Responsibilities
• Design high-performance, high-bandwidth Network-on-Chip (NoC) IP for advanced AI SoCs.
• Define microarchitecture specifications and develop synthesizable RTL using Verilog/SystemVerilog.
• Drive synthesis, timing constraints, CDC/Lint closure, and PPA optimization.
• Integrate IP across SoC subsystems and support post-silicon debug.
• Collaborate with architecture, verification, physical design, and SoC integration teams.
• Develop Python scripts for design automation and productivity.
Qualifications
• 8+ years delivering ASIC/SoC IP designs.
• 6+ years of hands-on digital design, RTL, and microarchitecture experience.
• Strong experience with Verilog/SystemVerilog, synthesis, timing constraints, CDC, Lint, and PPA trade-offs.
• Experience with NoC/interconnect and high-throughput/low-latency designs.
• Experience with SoC integration, post-silicon debug, and Python scripting.
Key Skills: ASIC | NoC | RTL | SystemVerilog | Microarchitecture | CDC | Lint | Synthesis | Timing | PPA | Python
Work Authorization: Applicants must be legally authorized to work in the United States.
Skills:
SoC,ASIC,Design Engineering
