Job Area:Engineering Group, Engineering Group > ASICS Engineering
General Summary:What we are doing what has not been done.Shape the future of low power AI subsystems.Push the boundaries on features and performance.Qualcomm Technologies Audio products are designed to offer premium wireless connectivity, high levels of integration, immersive sound quality, and on-device AI for smart audio and context aware applications. An ultra-low power subsystem within a low power SoC; a chip-within-a-chip HW block incorporating multiple always-on IP's, design execution within this group requires solving ground-breaking challenges and multiple power domain crossing issues.
As we are pioneer new and/or improved functionality, innovate to minimize power consumption. Make a difference, join a team on the cutting edge and become an integral part of Qualcomm's growth and momentum.
We are looking for an ASIC Implementation Engineer to be part of our team to innovate and design complex leading, ultra-low power, solutions for audio and context aware applications. We are open to all levels of applicants, with responsibility being commensurate with experience. We are looking for applicants who thrive when presented with constant opportunities for learning and growth and who want to have a large impact on our team.
New PositionAs part of our team your responsibilities will be focused on key ASIC implementation tasks such as:
- Synthesis
- Timing Constraints
- Implementing ECOs
- STA
- Power intent validation (CLP)
- Lint
- Power Analysis Tasks
- CDC validation
- Model and analyze performance, area, power, and system cost tradeoffs for different micro-architectures
- Contribute to implementation methodologies/ flows
Specific responsibilities will be a function of project and team needs and may vary over time. However, the initial focus of this role will be:
- CLP (RTL and/or netlist)
- PTPX / power pro
- Power analysis / optimization
In addition to implementation tasks the successful candidate may also be asked to perform ASIC design tasks including some RTL development.
Requirements:- 2 years of professional ASIC hardware design and/or implementation experience.
- Expertise with Verilog/VHDL RTL design languages and ability to write clean, readable, synthesizable RTL.
- Exceptional understanding of ASIC/VLSI concepts
- Experience in logic synthesis using Synopsis and/or Cadence tools.
- Detail oriented with strong analytical and debugging skills
Preferred Qualifications:- Strong communication (written and verbal) and collaboration skills
- Working knowledge of UPF specification
- Experience with synthesis, STA
- Experience with High-speed/Low power ASIC design within a Unix environment
- Experience with clock domain crossing techniques and tools
- Scripting skills (Python , PERL, TCL or C)
Minimum Qualifications:• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 1+ years of ASIC design, verification, or related work experience.
OR
PhD in Science, Engineering, or related field.
Pay range and Other Compensation & Benefits:$115,600.00 - $165,600.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer.
If you would like more information about this role, please contact Qualcomm Careers.
