We are seeking aASIC/SOCDesign Validationengineers(all levels including Senior, Principal, Senior Principal)towork in the Design Validation team whoarecritical to ensuring our RFIC/ASIC designsculminate in thoroughly validatedcutting-edge integrated circuits that drive Blue Origin's mission of enabling millions to live and work in space for the benefit of Earth.

Location:
This role is basedonsitein San Diego, CA; Bay Area, CA;Austin, TX; Kent, WA.

This role requires a highly skilled verification engineer with extensive experience across the full spectrum of pre-silicon and post-silicon verification for complex SoC designs. The candidate will be responsible for driving verification methodologies, managing test planning and coverage closure, and ensuring seamless portability across multiple verification environments including emulation, FPGA, and silicon bring-up. Strong expertise in System Verilog, DSP structures, modem SOCs, and interface protocols is essential, along with the ability to integrate and verify complex IPs and support software co-simulation across all platforms.

Pre-Silicon

• System Verilog experience in verifying complex SOCs
• Formal verification
• Functional coverage, definition and collection
• Module verification
• Complex subsystem verification
• Complex SoC verification
• Co-simulation with software, integration of software build tool flow with simulation
• Test planning and tracking, coverage closure
• Methodology and flow, definition and implementation
• Power estimation
• Gate simulation
• Performance analysis
• External IP integration
• AXI bus complex
• High performance NOC and DMA
• DDR, PCIE, Ethernet, SPI
• High speed SERDES
• DSP structures (FIR, Cordic, FFT/IFFT, MAC, circular buffers, analog-digital interface)
• Modern modem SOCs using innovative DSP, coding, framing (phy and MAC)
• Sequenced and time bound data movement in DSP structures (time slots, time stamps etc.)
• AMS verification
• SOC top level verification using models for analog macros
• Verification using golden reference models in MATLAB, SystemC or C
• Code coverage
• Emulators: qualification for release, compatibility of test cases, reproduce and debug failures, how to partition verification and assess coverage between this and simulation
• Portable verification across block level and top level, FPGA and ASIC, rtl and gate, pre-silicon and silicon/prototyping (lab bringup and test): common method for configuring, stimulus, checking, reusability across environments, methods for doing this efficiently

Post-Silicon

• Post silicon bring up
• Support for post-silicon and FPGA in the same pre-silicon environment (portable bench/sim platforms). Compatibility of test cases, reproduce and debug failures, accelerate software development

FPGA

• ASIC to/from FPGA flow
• Prototyping: qualification for release, different design configurations and top levels, compatibility of test cases, reproduce and debug failures, accelerate software development, how to partition verification and assess coverage between this and simulation

Minimum Qualifications:

• BS, MS in Electrical Engineering or a related technical field.
• 8+ years of experience.
• Deep working knowledge and hands on experience in innovative verification flows.