About the roleDesign the RTL that defines our AI accelerator. You'll architect and implement the digital blocks - compute datapath, memory subsystem, on-chip interconnect, and control logic - from microarchitecture spec through synthesis-ready, timing-clean RTL, and own those blocks end-to-end with architecture, DV, physical design, and DFT all the way to silicon.
What You'll Do:- Own RTL design of digital blocks/subsystems for our accelerator - microarchitecture definition, SystemVerilog implementation, and integration
- Translate architectural specs into efficient, synthesizable RTL that meets power/performance/area (PPA) targets
- Drive microarchitecture trade-offs - pipelining, datapath vs. control, clock/power gating - for high-performance, low-power design
- Partner with DV on verification, PD on synthesis/timing/floorplan closure, and DFT on testability
- Own block-level quality: synthesis, timing/constraints (SDC, STA), lint, and CDC signoff
- Contribute to architecture definition and design reviews; debug across simulation, emulation, and post-silicon bring-up
- Use and develop AI-assisted tool flows to accelerate design and verification
What We're Looking For- Strong digital-design fundamentals and expert Verilog/SystemVerilog RTL
- 5+ years designing complex digital blocks/SoCs taken to silicon
- Solid microarchitecture skills - pipelining, datapath/control, FIFOs, arbitration, memory subsystems, on-chip interconnect/NoC
- Synthesis & timing awareness - writing synthesizable RTL, SDC constraints, STA, clock/power gating, CDC, lint
- Demonstrated collaboration with DV, PD, and DFT across the full RTL2GDS flow to tapeout
- Scripting (Python/Tcl/) for design automation
- (Optional) AI/ML accelerator or high-performance compute-datapath design; low-power techniques (UPF); high-speed interfaces (HBM, PCIe, SerDes); advanced nodes (7nm or better); RISC-V/CPU design; FPGA prototyping
CompensationFinal offers depend on level, location, and skills relevant to the role. Additional compensation: equity grant per company guidelines; medical / dental / vision; 401(k); standard PTO.
Visa SponsorshipDensityAI sponsors qualified candidates for H-1B, O-1, TN, E-3, and other employment-based visas, and we welcome applicants on F-1 OPT and STEM-OPT. Work authorization is required at start; we provide immigration support to secure or transfer status.
Export ControlsAspects of this role may involve access to information subject to U.S. export controls (EAR/ITAR). We may discuss licensing or scope adjustments during the interview.
Full compensation packages are based on candidate experience and relevant certifications.
California pay range
$250,000-$375,000 USD
