Minimum qualifications:- Bachelor's degree in electrical engineering, computer engineering, computer science, or a related field, or equivalent practical experience.
- 4 years of experience with custom silicon design (e.g., SoCs, ASICs, etc.).
- Experience with RTL design using Verilog or SystemVerilog.
Preferred qualifications:- Master's degree or PhD in electrical engineering, computer engineering, or computer science, with a focus on computer architecture.
- Experience interacting with software, architecture, and other cross-functional teams.
- Experience with a scripting language (e.g., Python or Perl).
- Experience applying engineering best practices (e.g., code review, testing, refactoring).
- Knowledge of processor design, accelerators, or memory hierarchies and machine learning algorithms.
- Knowledge of high performance and low power design techniques.
About the jobIn this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $138000 - $198000 (USD) 15% bonus target equity benefits
Learn more about benefits at Google .
Responsibilities- Understand the overall application of the chip, proposing and developing improvements in overall design.
- Design and document one or more blocks of an ASIC, including functionality and timing.
- Work with software teams on functionality, interfaces, and documentation.
