Texas Instruments

RET/OPC Process Development Engineer

Texas Instruments$100K — $130K *
Manufacturing & Automotive
5 - 7 years of experience
Job Overview by Ladders

Qualifications

  • Master's degree in Electrical Engineering, Physics, Materials Science, or a related field.
  • Minimum of 5 years’ experience in design retargeting, OPC, or physical design within semiconductor or EDA environments.
  • Strong grasp of optical lithography principles, RET techniques (e.g., OPC, SRA, assist features), and mask technology.
  • Proven hands-on experience with industry-standard OPC software tools such as Synopsys Sentaurus Lithography, Mentor Calibre, or ASML Brion.
  • Proficiency in scripting with common programming languages.
  • Familiarity with layout editing/verification tools (e.g., Calibre, Virtuoso, ICC2) and challenges associated with advanced nodes (28nm/22nm).

Responsibilities

  • Develop and implement design retargeting strategies to convert customer design intent into manufacturable layouts.
  • Collaborate with OPC, lithography, and process integration teams to ensure precise pattern transfer and high-yield manufacturing.
  • Analyze and modify layout geometries to improve printability and enhance process window robustness.
  • Automate retargeting flows using EDA tools and integrate them into the tape-out pipeline.
  • Provide customer design enablement by offering feedback on layout constraints and manufacturability guidelines.
  • Utilize CD metrology, SEM reviews, and simulation data to refine retargeting rules.
  • Mentor junior engineers and contribute to evolving design rules and patterning strategies for advanced nodes.

Benefits

  • Empowerment to own your career and professional development.
  • A diverse, collaborative work environment that values multiple perspectives.
  • Competitive pay and comprehensive benefits focused on overall well-being.
Full Job Description
Job Description

Job Description:

We are seeking a highly skilled and motivated Design Retargeting Engineer to join our RET(Resolution Enhancement Team) in ATD. In this role, you will be responsible for translating customer design intent into manufacturable layouts by applying advanced retargeting techniques. You will work at the intersection of design and process, ensuring that physical layouts are optimized for yield, performance, and manufacturability across various technology nodes.

Responsibilities:
  • Develop and implement design retargeting strategies to bridge the gap between design intent and process capabilities.
  • Collaborate with OPC, lithography, and process integration teams to ensure accurate pattern transfer and high-yield manufacturing.
  • Analyze and modify layout geometries to improve printability and process window robustness.
  • Work with EDA tools to automate retargeting flows and integrate them into the tape-out pipeline.
  • Support customer design enablement by providing feedback on layout constraints and manufacturability guidelines.
  • Perform data analysis using CD metrology, SEM review, and simulation results to refine retargeting rules.
  • Contribute to the development of design rules and patterning strategies for advanced nodes (e.g., 28nm, 22nm).
  • Mentor junior engineers and contribute to knowledge sharing within the team.


Qualifications

Qualifications:
  • Master's in Electrical Engineering, Physics, Materials Science, or a related field.
  • 5+ years of experience in design retargeting, OPC, or physical design in a semiconductor or EDA environment.
  • Strong understanding of optical lithography principles, RET (e.g., OPC, SRA, assist features), and mask technology.
  • Hands-on experience with industry-standard OPC software tools (e.g., Synopsis Sentaurus Lithography, Mentor Calibre, ASML Brion).
  • Proficiency in scripting with any scripting languages
  • Familiarity with layout editing and verification tools (e.g., Calibre, Virtuoso, ICC2).
  • Understanding of lithography, patterning, and process integration challenges in advanced nodes.
  • Familiarity with 28nm/22nm process limitations and lithographic constraints.

Preferred Qualifications:
  • PhD in Electrical Engineering, Physics, Materials Science, or a related field.
  • Experience with advanced technology nodes (e.g., 45nm, 28nm, 22nm, and 20nm ).
  • Solid knowledge of semiconductor device physics and fabrication processes.
  • Experience in analog layout interaction with lithography and OPC flows.
  • Experience with statistical data analysis and yield improvement methodologies.
  • Strong analytical and problem-solving skills.
  • Ability to work effectively in a cross-functional team environment.
  • Excellent problem-solving, analytical, and communication skills.
  • Knowledge of design rule checking (DRC) and layout versus schematic (LVS).
  • Knowledge of Design Technology Co-Optimization (DTCO)
  • Exposure to machine learning or data-driven approaches for layout optimization.


About the Team

TI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.

About Texas Instruments

National Semiconductor is a semiconductor manufacturer, specializing in analog devices and subsystems, headquartered in Santa Clara, California. The products of National Semiconductor include power management circuits, display drivers, audio and operational amplifiers, communication interface products and data conversion solutions. National's key markets include wireless handsets, displays and a variety of broad electronics markets, including medical, automotive, industrial, and test and measurement applications.

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31,000 employees
Market Cap
$148.9 billion
Industry
Net Income
$5.5 billion
Founded
1930
5 Year Trend
+6.5%
Revenue
$14.4 billion
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