Synopsys Inc

R&D Engineering, Principal Engineer

Synopsys Inc$162K — $195K *
Technical Services
8 - 10 years of experience
Job Overview by Ladders

Qualifications

  • MS or PhD in Electrical Engineering, Computer Engineering, Computer Science, or equivalent expertise.
  • 10+ years of experience in EDA, system software, or related technical domains.
  • Deep hands-on experience with static timing analysis or related circuit analysis technologies.
  • Expert-level proficiency in C/C++ within large, performance-critical codebases.
  • Track record of architecting complex systems and defining long-term technical strategies.
  • Strong knowledge in algorithms, data structures, and numerical analysis at scale.
  • Ability to independently drive technical strategy and architectural decisions.

Responsibilities

  • Owning and evolving major architectural components of PrimeTime and its timing engines.
  • Defining long-term technical strategy for static timing analysis accuracy and capacity.
  • Driving architectural consistency across PrimeTime and related integrations.
  • Leading design and implementation of STA algorithms for multi-billion-cell designs.
  • Resolving technical issues and balancing accuracy, performance, and usability at sign-off.
  • Acting as the technical authority for customer escalations and architectural challenges.
  • Mentoring engineers and raising the technical bar through reviews and discussions.

Benefits

  • Comprehensive health, wellness, and financial benefits to cater to your needs.
  • Monetary and non-monetary offerings as part of a total rewards package.
  • Eligibility for annual bonuses and discretionary bonuses.
  • Options for equity participation in the company.
Full Job Description
Descriptions & Requirements

Job Description and Requirements

You Are:

You are passionate about advancing the boundaries of electronic design automation (EDA) and static timing analysis (STA). Combining deep domain knowledge with practical hands-on experience, you thrive in architecting complex systems that impact the global semiconductor industry. You possess a strong sense of ownership, are comfortable navigating ambiguity, and excel at resolving the most challenging technical problems. Your expertise enables you to analyze system-level tradeoffs, balancing accuracy, scalability, and performance for mission-critical sign-off flows. You are a collaborative influencer--valued for your ability to mentor and guide both senior and junior engineers, and for your skill in articulating architectural direction that aligns with business goals and industry trends.

You are recognized for your proficiency in C/C++ and your ability to design and implement scalable, high-performance codebases. You are adept at identifying systemic issues and providing principled solutions, especially when working directly with customers on tapeout-critical challenges. Your communication skills foster trust and inspire technical excellence across distributed teams. You are proactive in defining long-term strategies and have a proven track record of delivering impactful results in complex, fast-paced environments. Above all, you are driven by a desire to shape the future of silicon innovation, ensuring that the PrimeTime platform remains the industry standard for timing sign-off at advanced technology nodes.

What You'll Be Doing:

* Owning and evolving major architectural components of PrimeTime, including timing engines, path search frameworks, constraint modeling, and distributed/parallel analysis flows.
* Defining long-term technical strategy for accuracy, capacity, runtime, and extensibility in static timing analysis, collaborating closely with senior R&D leadership.
* Driving architectural consistency across PrimeTime, Fusion Compiler integration points, and broader sign-off ecosystems.
* Leading the design and implementation of next-generation STA algorithms addressing multi-billion-cell designs, advanced timing effects, and non-linear behaviors.
* Resolving cross-cutting technical issues and making principled tradeoffs between accuracy, performance, memory footprint, and usability at sign-off.
* Acting as the go-to technical authority for customer escalations, sign-off discrepancies, and complex architectural challenges.
* Diagnosing systemic issues involving SDC interpretation, timing convergence, path pessimism/optimism, and tool correlations across flows.
* Mentoring and influencing engineers through technical reviews, discussions, and leadership--raising the technical bar across the organization.

The Impact You Will Have:

* Shape the architectural direction of PrimeTime, ensuring it remains the industry-leading STA solution for advanced silicon designs.
* Define how PrimeTime scales to meet the complexity and reliability demands of next-generation SoCs.
* Reduce customer risk at tapeout by delivering architectural correctness, predictability, and performance.
* Serve as a technical pillar for a tool that is crucial to the success of global silicon innovation.
* Influence the technical roadmap for sign-off methodology, driving improvements across multiple product releases.
* Enhance collaboration across distributed teams, fostering a culture of technical excellence and innovation.
* Directly impact customer satisfaction by resolving tapeout-critical issues and ensuring robust timing sign-off flows.

What You'll Need:

* MS or PhD in Electrical Engineering, Computer Engineering, Computer Science, or equivalent demonstrated industry expertise.
* 10 years + of experience in EDA, system software, or similarly demanding technical domains.
* Deep hands-on experience with STA or closely related timing/circuit analysis technologies.
* Expert-level proficiency in C/C++ within large, performance-critical codebases.
* Proven track record of architecting complex systems and defining multi-year technical initiatives.
* Strong foundation in algorithms, data structures, and numerical analysis applied at scale.
* Ability to independently define, justify, and drive technical strategy and architectural decisions.
* Preferred: Experience with PrimeTime, distributed computing, parallel STA, memory-scalable design, and advanced-node design challenges.

Who You Are:

* Strategic thinker with a strong sense of ownership and accountability.
* Collaborative influencer, able to mentor and inspire technical teams.
* Excellent communicator, capable of articulating complex technical concepts to diverse audiences.
* Resilient problem solver who thrives on tackling challenging, high-impact issues.
* Adaptable and proactive, comfortable working in fast-paced and evolving environments.
* Detail-oriented yet able to see the bigger picture, balancing short-term needs with long-term vision.

The Team You'll Be A Part Of:

You will join a world-class R&D team dedicated to advancing the PrimeTime platform, collaborating with experts in static timing analysis, algorithm design, and EDA systems. The team is passionate about delivering innovative solutions that define industry standards for timing sign-off. Together, you will tackle complex architectural challenges, drive technical excellence, and shape the future of silicon design by enabling customers to achieve reliable and high-performance tapeouts.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

#TPG

In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.

About Synopsys Inc

Synopsys, Inc. is an American electronic design automation company that focuses on silicon design and verification, silicon intellectual property and software security and quality. Products include logic synthesis, behavioral synthesis, place and route, static timing analysis, formal verification, hardware description language (SystemC, SystemVerilog/Verilog, VHDL) simulators, as well as transistor-level circuit simulation. The simulators include development and debugging environments which assist in the design of the logic for chips and computer systems.
Learn more about Synopsys Inc
Size
16,361 employees
Market Cap
$48.6 billion
Industry
Net Income
$722.6 million
Founded
1986
5 Year Trend
+13.3%
Revenue
$3.8 billion
NASDAQ

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