Job Duties:- Research, design, develop, and test electronic components and systems for Electronic Design Automation (EDA) and semiconductor intellectual property (IP) employing knowledge of electronic theory and materials properties.
- Research, design, develop, and test algorithms and features of Cadence's EDA tools (Innovus and Genus) and improve tool quality by employing knowledge of electronic theory and semiconductor materials properties.
- Define and establish industry leading flows and methodologies for Digital Design performance, power, area (PPA), and Design Rule Check (DRC) closure using Cadence's products.
- Run design benchmark and develop flows and solutions.
- Work closely with key customers on critical projects deploying Cadence's established quality of results (PPA) closure methodologies.
- Collaborate with Research & Development (R&D) to improve Cadence's products to maintain the company's leading edge in the market.
- Provide guidance to field organization on the latest tool features and computer processing unit timing closure methodologies.
- Track and debug customer issues and work with R&D and release team on issue resolution.
- Evaluate project work to ensure effectiveness, technical adequacy, or compatibility in the resolution of complex electronics engineering problems and confer with engineers and customers to discuss existing or potential electronics engineering projects.
- Some telecommuting permitted.
Qualifications: - Master's degree in Electrical Engineering, Electronic Engineering, or related field
- Minimum three (3) years of experience in the job offered or in a related engineering occupation.
- Digital physical design using Cadence's Innovus and Genus tools
- Utilize programming languages like TCL, Perl, or Python to create automation scripts for debugging and automating data processing workflows
- Using AI-driven EDA tools such as Cerebrus and JEDAI to achieve better performance/power/area on critical designs
- Design of high-performance GPUs and CPUs of N2 node, and optimizing timing to achieve a higher speed of the chip
- Power optimization in design architectures and development flows using Cadence Joules
- Conducting in-depth analysis of designs at advanced technology nodes including N2, N3, and N5, to identify areas for power efficiency improvements
- Analyzing and architecting clock tree structures to meet design-specific timing, power, and area requirements
- Optimizing clock distribution networks to minimize skew, jitter, and latency, ensuring robust timing closure and efficient performance across various process, voltage, and temperature (PVT) corners.
The annual salary range for California is $171,704 to $253,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the base salary range is a guideline, and individual total compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
