Cadence Design Systems

Solutions Architect - AE

Cadence Design Systems$216K — $331K *
Technical Services
11 - 15 years of experience
Job Overview by Ladders

Qualifications

  • Bachelor's degree in Electronic Engineering, Electrical Engineering or related field.
  • Minimum 13 years of post-baccalaureate experience in EDA or related field.
  • Expertise in Synthesis, Place and Route for optimization of Power, Performance, and Area.
  • Experience developing tools for advanced process nodes (sub 4nm) using ASIC design skills.
  • Proficient in EDA IC digital implementation and signoff techniques.
  • Familiarity with Cadence tools for high performance core closure and trade-offs in performance.
  • Knowledge of chiplet design, system planning, and future design analysis.

Responsibilities

  • Research, design, and test electronic components and systems for EDA and semiconductor IP.
  • Implement netlist using 3D IC flow, demonstrating design convergence.
  • Analyze chiplet Signal Integrity and Power Integrity, providing design solutions.
  • Develop timing analysis methodology for 3DIC supporting heterogeneous chiplets.
  • Set up 3DIC flow for optimal chiplet communication.
  • Analyze chiplet floorplans to minimize connections between chiplets.
  • Be open to telecommuting and travel for projects across the United States.

Benefits

  • Paid vacation and paid holidays.
  • 401(k) plan with employer match.
  • Employee stock purchase plan.
  • Variety of medical, dental, and vision plan options.
Full Job Description
Job Duties:

  • Research, design, develop, and test electronic components and systems for Electronic Design Automation (EDA) and semiconductor intellectual property (IP) employing knowledge of electronic theory and materials properties.
  • Implement the netlist through 3D Integrated Circuit (IC) flow and showcase design convergence.
  • Work on chiplet Signal Integrity (SI) and Power Integrity (PI) analysis and provide engineering and design fixes to meet specifications.
  • Develop timing analysis flow and methodology for 3DIC to support heterogenous chiplets.
  • Responsible for 3DIC flow setup to achieve best chiplet partitioning for optimal chip-to-chip communication.
  • Analyze different chiplet floorplan for minimal distance/connection between chiplets.
  • Some telecommuting permitted.
  • Must be available to work on projects at various, unanticipated sites throughout the United States.


Qualifications:

  • Bachelor's degree in Electronic Engineering, Electrical Engineering or related field.
  • Minimum thirteen (13) years of progressive, post-baccalaureate experience in the job offered or in a related occupation.
  • Utilizing knowledge in Synthesis, Place and Route, and design closure techniques to demonstrate best Power-Performance-Area optimization;
  • Developing tools and methodologies for handling advance process node needs sub 4nm across different foundries using ASIC design skills;
  • Utilizing EDA's best available solution in the space of IC digital implementation and signoff to drive solution to address new problems and improve productivity;
  • Performing high performance core closure using Cadence Synthesis and Place and Route solution to performance power vs. power vs. area trade-off;
  • Utilizing signoff domain (extraction, timing, and emir) to drive full flow (rtl2gds);
  • Utilizing chiplet design, system planning, and analysis for future designs;
  • Full chip and sub system floor planning and clock design.
  • Must be available to work on projects at various, unanticipated sites throughout the United States.

The annual salary range for California is $216,091 to $331,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the base salary range is a guideline, and individual total compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

About Cadence Design Systems

Cadence Design Systems, Inc. is an American multinational electronic design automation software and engineering services company, founded in 1988 by the merger of SDA Systems and ECAD, Inc. The company produces software, hardware and silicon structures for designing integrated circuits, systems on chips (SoCs) and printed circuit boards.
Learn more about Cadence Design Systems
Size
9,300 employees
Market Cap
$43.9 billion
Industry
Net Income
$590.6 million
Founded
2018
5 Year Trend
+10.5%
Revenue
$2.6 billion
NASDAQ

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