Astera Labs

Product Applications Engineer (NCG 2026)

Astera Labs$140K — $150K *
Technical Services
Less than 5 years of experience
Job Overview by Ladders

Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Science, or related field; Master's preferred
  • Proficiency in C for embedded firmware in RTOS environments
  • Proficiency in Python for scripting and automation
  • Strong debugging skills in embedded systems
  • Familiarity with SoC interfaces like DDR and PCIe controllers
  • Technical writing for clear documentation

Responsibilities

  • Assist customers with Leo CXL Smart Memory Controllers bring-up and issue resolution
  • Develop, validate, and debug firmware using C and Python
  • Oversee end-to-end validation of DDR4/DDR5 interfaces
  • Collaborate with cross-functional teams to ensure timely delivery of collateral
  • Maintain Python-based automation and diagnostic tools
  • Contribute to technical documentation for internal and customer use

Benefits

  • Work onsite at San Jose, CA fostering collaboration
  • Opportunities for direct customer engagement
  • Chance to influence product innovation through customer feedback
  • Engage in hands-on laboratory work with cutting-edge technology
  • Collaborative environment with cross-functional teams
Full Job Description
Job Description:

As an Astera Labs Firmware Product Application Engineer, you will sit at the intersection of firmware engineering and customer-facing technical engagement. You will help enable Leo CXL Smart Memory Controllers at hyperscale customers and OEM partners - assisting with firmware bring-up, validation, and customer issue resolution from early silicon through production ramp.

You will help to provide technical guidance to customers to overcome design challenges, generate collateral for existing and new products, and drive innovation by providing insightful feedback to other internal teams to continuously improve products and processes. There are opportunities to support key customers directly, and also to dive deep in the lab to address the challenges associated with leading edge semiconductor products.

This position is required onsite in San Jose, CA.

Key Responsibilities
  • Assist with customer engagements for Leo CXL Smart Memory Controllers, including bring-up support, feature enablement, and issue triage on customer platforms
  • Develop, validate, and debug firmware using C and Python across Leo's PCIe/CXL and DDR memory subsystems
  • Assist with end-to-end firmware validation of DDR4/DDR5 DRAM interfaces, including initialization, training, RAS (Reliability, Availability, Serviceability) features, and performance tuning
  • Collaborate with cross-functional teams (FW engineering, HW, systems, product management) to help deliver firmware releases and customer collateral on schedule
  • Develop and maintain Python-based test scripts, automation frameworks, and diagnostic tools to support validation and customer debug workflows
  • Contribute to technical documentation including application notes, release notes, design guides, and customer-facing collateral


Basic Qualifications
  • Bachelor's degree in Electrical Engineering, Computer Science, or a related technical field; Master's degree preferred
  • Professional attitude with the ability to prioritize a dynamic list of tasks and work with minimal guidance
  • Entrepreneurial, open-minded behavior and can-do attitude - think and act fast with the customer in mind!
  • Authorized to work in the US and available to start immediately

Required Experience
  • Proficiency in C for embedded firmware development in RTOS environments
  • Proficiency in Python for scripting, test automation, and diagnostic tooling
  • Knowledge with firmware bring-up, debug, and validation of memory or I/O subsystems on server platforms
  • Strong debugging skills with the ability to triage and root-cause issues in complex embedded systems
  • Familiarity with SoC interfaces including DDR controllers, PCIe controllers, and on-chip memory subsystems
  • Knowledge of developer workflows: SCM (preferably Git), code reviews, CI/CD pipelines
  • Technical writing skills to generate clear, precise documentation including application notes and similar guides for internal and customer-facing audiences.

Preferred experience
  • Working knowledge of CXL (Compute Express Link) - CXL 1.1/2.0/3.0 - including memory expansion, pooling, and sharing concepts
  • Experience with PCIe endpoint firmware at the PHY, Link, and Transaction layers; familiarity with PCIe enumeration, MSI/MSI-X, SR-IOV, and error handling
  • Knowledge of high-speed memory interfaces - DDR4 and/or DDR5 DRAM - including initialization sequences, training algorithms, timing margins, and ECC/RAS features
  • Hands-on experience with PCIe/CXL protocol analyzers, BERT, and other lab debug equipment
  • Familiarity with BIOS/BMC/OS interactions with PCIe/CXL devices and MMIO/RAS concepts
  • Experience with server memory performance tuning - latency and bandwidth optimization
  • Prior customer-facing or field applications experience in a semiconductor or systems company is a strong plus


The base pay for this range is between $140,000 - $150,000 dependent on education level.

About Astera Labs

Astera Labs is a semiconductor company that designs and develops purpose-built connectivity solutions for data-centric systems. The company's portfolio of products includes system-aware semiconductor integrated circuits (ICs), boards, and intellectual property (IP) that are used in data center servers, storage, and networking equipment. Astera Labs' products are designed to improve the performance, latency, and power consumption of data-centric systems. The company was founded in 2018 and is headquartered in Santa Clara, California.
Learn more about Astera Labs
Size
51 employees
Industry
Net Income
-$3 million
Founded
2018
Revenue
$5 million
NASDAQ

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