Principal Physical Design Engineer
This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office.
Job Description:SoC Top-Level & block-level Physical Design EngineerAs a block-level and top-level SOC Physical Design Engineer, you will contribute to all phases of physical design from RTL to the delivery of our final GDSII. Your responsibilities include:
Responsibilities: - Implement physical design at the large SoC chip level from RTL to GDSII, creating a design database ready for manufacturing.
- Interact with IP vendors to understand IP integration requirements and integrate all blocks, IPs, and sub-chips at a large SoC level.
- Collaborate with the packaging team on Microbump/Probe Bump/Bump/Pad placement.
- Build full chip floorplan, including pads/ports/bump placement, block placement and optimization, block pins placement and alignment, power grid, and RDL design, etc.
- Develop the chip-level clock network and clock stations in collaboration with clock experts.
- Budget timing among blocks and sub-chips at the chip level, generating block/chip-level static timing constraints.
- Arrange, analyze, and optimize feedthrough and repeaters among all blocks/sub-chips at the chip level.
- Perform block-level place and route, including custom place & route, ensuring the design meets timing, area, power constraints, and all sign-off criteria.
- Generate and implement ECOs to fix timing, signal integrity, EM/IR violations, PV, and complete formal verification.
- Integrate DFT into physical design, ensuring alignment with overall test strategies and manufacturing requirements.
- Run Physical Design verification flow at chip/block level, fixing LVS/DRC/ERC/ANT violations.
- Collaborate closely with architecture, frontend design, DV, and package teams to ensure cohesive design implementation and successful project tapeouts.
Minimum Qualifications: Education: - BS degree in electrical engineering, computer engineering, or a related field with 7+ years of experience in block or full-chip physical design, or
- MS degree in the above fields with 5+ years of related experience.
Technical Expertise: - Deep design experience in large SoC designs, including IP integration, padring design, bump planning, and RDL routing strategy.
- Extensive knowledge and practices in Physical Design, including physically aware synthesis, floor-planning, place & route, CTS, and repeater/feedthrough.
- Experience in developing and implementing power-grid and clock network at chip level.
- Knowledge of basic SoC architecture and HDL languages like Verilog to work with the logic design team for timing fixes.
- Experience in physical design verification to debug LVS/DRC/ERC/ANT issues at chip/block level.
- Experience in custom place and route.
- Exposure to 2.5D/3D packaging is preferred.
- High performance and large chip design experience is preferred.
- Exposure to DFT is preferred.
- Proficiency in writing Linux shell scripts in Perl, TCL, and Python.
- Real chip tapeout experience in 7nm and/or below with a successful signoff track record.
- Self-motivated with strong problem-solving and debugging skills.
- Ability to work effectively in a dynamic group environment.
What We Can Offer You:Health & WellbeingWe strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.
Personal & Professional DevelopmentWe also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have - whether you want to become a knowledge expert in your field or apply your skills to another division.
Unconditional InclusionWe are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.
Let's Stay Connected:Follow @HPECareers on Instagram to see the latest on people, culture and tech at HPE.
#unitedstates
Job:Engineering
Job Level:TCP_05
"The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level.
- United States of America: Annual Salary USD 174,000 - 352,500 in California
The listed salary range reflects base salary. Variable incentives may also be offered."
Information about employee benefits offered in the US can be found at https://myhperewards.com/main/new-hire-enrollment.html
