Responsibilities & SkillsLattice Semiconductor is seeking a Principal Engineer to join the team responsible for the architecture, design, and development of advanced EDA software tools for Lattice FPGA platforms. This role is central to delivering high-quality, scalable synthesis solutions across the Lattice product portfolio, with primary ownership of the Lattice synthesis toolchain.The ideal candidate is a technical leader and domain expert in FPGA synthesis engine design, with a deep understanding of how to achieve best-in-class results for specific FPGA architectures. You will drive industry-leading outcomes across maximum frequency (Fmax), area efficiency, runtime performance, and memory utilization—balancing tradeoffs to meet the demands of diverse customer use cases.This role carries significant responsibility for enabling next-generation FPGA architectures, ensuring synthesis solutions scale effectively and remain competitive as the Lattice platform roadmap evolves.
Key Responsibilities
- Provide technical leadership in the design, implementation, and optimization of FPGA synthesis engines across multiple Lattice product families
- Collaborate with synthesis developers and cross-functional partners to define architecture, algorithms, and long-term technical direction
- Drive quality-of-results (QoR) improvements spanning Fmax, area, and compile time
- Lead development and enablement of new synthesis features and capabilities aligned with product roadmap priorities
- Maintain, enhance, and modernize the synthesis codebase to ensure robustness, scalability, and long-term maintainability
- Serve as the technical escalation point for complex synthesis issues, including customer-reported problems
- Influence engineering best practices, code quality, and design standards within the synthesis team
- Mentor and guide junior and mid-level engineers through design reviews and technical guidance
Required Qualifications
- 10+ years of experience in EDA software development, with a focus on logic synthesis or place-and-route
- Expert-level proficiency in C++, with a track record of designing, implementing, and optimizing large-scale, performance-critical software systems
- Deep knowledge of synthesis algorithms — including technology mapping, retiming, logic optimization, and timing-driven optimization
- Strong understanding of FPGA architectures (LUTs, DSPs, BRAMs, carry chains) and how architectural constraints inform synthesis strategy
- Experience with QoR benchmarking methodologies and data-driven optimization workflows
- Demonstrated ability to lead technical initiatives independently and influence without direct authority
- Hands-on experience with generative AI tools applied to developer productivity — debugging, code review, algorithm exploration, or documentation
Preferred Qualifications
- Familiarity with the Lattice synthesis toolchain (Radiant, Propel, or ACE environments)
- Experience with Python scripting for automation, regression testing, or QoR analysis
- M.S. or Ph.D. in Computer Science, Electrical Engineering, or a related field
